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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 22:54:35 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-25 09:34:19 -0700 |
| commit | 609535739036c30efc35a57730e5ffe968267cdb (patch) | |
| tree | b4c0a4ebff983a55283443e78df932a8db0aaccc /techlibs/xilinx/abc_xc7.box | |
| parent | 6f36ec8ecf147f8d669f35dd616714af971db6f4 (diff) | |
| download | yosys-609535739036c30efc35a57730e5ffe968267cdb.tar.gz yosys-609535739036c30efc35a57730e5ffe968267cdb.tar.bz2 yosys-609535739036c30efc35a57730e5ffe968267cdb.zip | |
Add RAM32X1D box info
Diffstat (limited to 'techlibs/xilinx/abc_xc7.box')
| -rw-r--r-- | techlibs/xilinx/abc_xc7.box | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index 8c046cdbc..1a7243f54 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -31,15 +31,22 @@ CARRY4 3 1 10 8 580 526 507 398 385 508 528 378 380 114 # SLICEM/A6LUT +# Inputs: A0 A1 A2 A3 A4 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 WCLK WE +# Outputs: DPO SPO +RAM32X1D 4 0 13 2 +- - - - - - 124 124 124 124 124 - - +124 124 124 124 124 - - - - - - - - + +# SLICEM/A6LUT # Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE # Outputs: DPO SPO -RAM64X1D 4 0 15 2 +RAM64X1D 5 0 15 2 - - - - - - - 642 631 472 407 238 127 - - 642 631 472 407 238 127 - - - - - - - - - # SLICEM/A6LUT + F7[AB]MUX # Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE # Outputs: DPO SPO -RAM128X1D 5 0 17 2 +RAM128X1D 6 0 17 2 - - - - - - - - 1009 998 839 774 605 494 450 - - 1047 1036 877 812 643 532 478 - - - - - - - - - - |