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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-19 18:59:28 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-19 18:59:28 -0700 |
| commit | e09f80479e6d16cf95c26e406bf06d81b94231f4 (patch) | |
| tree | 44e0ac0df9cfb0801bf919a75d2e70a61bbdb7d4 /techlibs/xilinx/abc_unmap.v | |
| parent | 362a803779ac1a8a3af1e4991b80b0c4c71e02ff (diff) | |
| download | yosys-e09f80479e6d16cf95c26e406bf06d81b94231f4.tar.gz yosys-e09f80479e6d16cf95c26e406bf06d81b94231f4.tar.bz2 yosys-e09f80479e6d16cf95c26e406bf06d81b94231f4.zip | |
Fix DSP48E1 timing by breaking P path if MREG or PREG
Diffstat (limited to 'techlibs/xilinx/abc_unmap.v')
| -rw-r--r-- | techlibs/xilinx/abc_unmap.v | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc_unmap.v index 010041b73..137829d65 100644 --- a/techlibs/xilinx/abc_unmap.v +++ b/techlibs/xilinx/abc_unmap.v @@ -32,12 +32,14 @@ module \$__ABC_DSP48E1_REG (input [47:0] I, output [47:0] O, output Q); endmodule (* techmap_celltype = "$__ABC_DSP48E1_MULT_P_MUX $__ABC_DSP48E1_MULT_PCOUT_MUX $__ABC_DSP48E1_MULT_DPORT_P_MUX $__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX $__ABC_DSP48E1_P_MUX $__ABC_DSP48E1_PCOUT_MUX" *) module \$__ABC_DSP48E1_MUX ( - input Aq, Bq, Cq, Dq, ADq, Mq, + input Aq, Bq, Cq, Dq, ADq, + input [47:0] I, + input Mq, input [47:0] P, input Pq, output [47:0] O ); - assign O = P; + assign O = I; endmodule (* techmap_celltype = "$__ABC_DSP48E1_MULT $__ABC_DSP48E1_MULT_DPORT $__ABC_DSP48E1" *) |