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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-16 10:42:00 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-16 10:42:00 -0700 |
| commit | 0c59bc0b75ba2985e6ae0806d410fe2fa1c94e37 (patch) | |
| tree | be0fd326e57bb5bb5e9b559f4573c220fdb03078 /techlibs/xilinx/abc_ff.v | |
| parent | 59dcfcc9193160302e1f8ca2e95b473241b1752a (diff) | |
| download | yosys-0c59bc0b75ba2985e6ae0806d410fe2fa1c94e37.tar.gz yosys-0c59bc0b75ba2985e6ae0806d410fe2fa1c94e37.tar.bz2 yosys-0c59bc0b75ba2985e6ae0806d410fe2fa1c94e37.zip | |
Cleanup
Diffstat (limited to 'techlibs/xilinx/abc_ff.v')
| -rw-r--r-- | techlibs/xilinx/abc_ff.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v index abf4ac093..e95602ab2 100644 --- a/techlibs/xilinx/abc_ff.v +++ b/techlibs/xilinx/abc_ff.v @@ -23,11 +23,11 @@ module \$__ABC_FF_ (input C, D, output Q); endmodule -(* abc_box_id = 6, lib_whitebox, abc_flop *) -module \$__ABC_FDRE ((* abc_flop_q *) output Q, input C, CE, (* abc_flop_d *) input D, (* abc_flop_q_past, abc_discard *) input Q_past, input R); +(* abc_box_id = 6, lib_whitebox, abc_flop = "FDRE", abc_flop_q = "Q", abc_flop_d = "D", abc_flop_past_q = "\\$pastQ" *) +module \$__ABC_FDRE (output Q, input C, CE, D, R, \$pastQ ); parameter [0:0] INIT = 1'b0; //parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_R_INVERTED = 1'b0; - assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : Q_past); + assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ ); endmodule |