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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-19 11:23:41 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-19 11:23:41 -0800 |
| commit | 979bf36fb00ec61ec7e27f074079e0464be03be7 (patch) | |
| tree | faa093c9b23663280a59b32fe0f5fa4137fb7864 /techlibs/xilinx/abc9_unmap.v | |
| parent | 94f15f023c8720d84211ac75980cf0b0f492411d (diff) | |
| download | yosys-979bf36fb00ec61ec7e27f074079e0464be03be7.tar.gz yosys-979bf36fb00ec61ec7e27f074079e0464be03be7.tar.bz2 yosys-979bf36fb00ec61ec7e27f074079e0464be03be7.zip | |
Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t
Diffstat (limited to 'techlibs/xilinx/abc9_unmap.v')
| -rw-r--r-- | techlibs/xilinx/abc9_unmap.v | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/techlibs/xilinx/abc9_unmap.v b/techlibs/xilinx/abc9_unmap.v index 21fe78d08..46526007d 100644 --- a/techlibs/xilinx/abc9_unmap.v +++ b/techlibs/xilinx/abc9_unmap.v @@ -20,7 +20,8 @@ // ============================================================================ -module \$__ABC9_ASYNC (input A, S, output Y); +(* techmap_celltype = "$__ABC9_ASYNC0 $__ABC9_ASYNC1" *) +module \$__ABC9_ASYNC01 (input A, S, output Y); assign Y = A; endmodule |