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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-02 12:32:27 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-03-02 12:32:27 -0800 |
| commit | 4f889b2f57b732083dd4bf336a0d361f70e5b2d0 (patch) | |
| tree | 5f8e46c0273e9e9bee1d6e6a6775b3f58ec302da /techlibs/xilinx/abc9_unmap.v | |
| parent | b1e248b0e6c7945870c83ac82bfb4ed8e9d8ff66 (diff) | |
| parent | 090e54569a58b26d616806337c28507d199ca43c (diff) | |
| download | yosys-4f889b2f57b732083dd4bf336a0d361f70e5b2d0.tar.gz yosys-4f889b2f57b732083dd4bf336a0d361f70e5b2d0.tar.bz2 yosys-4f889b2f57b732083dd4bf336a0d361f70e5b2d0.zip | |
Merge pull request #1724 from YosysHQ/eddie/abc9_specify
abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
Diffstat (limited to 'techlibs/xilinx/abc9_unmap.v')
| -rw-r--r-- | techlibs/xilinx/abc9_unmap.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/abc9_unmap.v b/techlibs/xilinx/abc9_unmap.v index f2342ce62..c02cc196a 100644 --- a/techlibs/xilinx/abc9_unmap.v +++ b/techlibs/xilinx/abc9_unmap.v @@ -29,10 +29,10 @@ module $__ABC9_FF_(input D, output Q); assign Q = D; endmodule -module $__ABC9_LUT6(input A, input [5:0] S, output Y); +module $__ABC9_RAM6(input A, input [5:0] S, output Y); assign Y = A; endmodule -module $__ABC9_LUT7(input A, input [6:0] S, output Y); +module $__ABC9_RAM7(input A, input [6:0] S, output Y); assign Y = A; endmodule |