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authorClifford Wolf <clifford@clifford.at>2018-10-31 15:36:53 +0100
committerClifford Wolf <clifford@clifford.at>2018-10-31 15:36:53 +0100
commitd084fb4c3f389b99c08909666d8e953017cb7656 (patch)
treeac126930d2dc5a418c85a5ff52aba9dd6dbd05ce /techlibs/sf2/cells_sim.v
parentcf79fd43761b6501f392ee6ad4ed0f961b93a56f (diff)
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Fix sf2 LUT interface
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'techlibs/sf2/cells_sim.v')
-rw-r--r--techlibs/sf2/cells_sim.v16
1 files changed, 8 insertions, 8 deletions
diff --git a/techlibs/sf2/cells_sim.v b/techlibs/sf2/cells_sim.v
index 89b8c55fd..b03b2c750 100644
--- a/techlibs/sf2/cells_sim.v
+++ b/techlibs/sf2/cells_sim.v
@@ -37,39 +37,39 @@ module SLE (
endmodule
module CFG1 (
- output O,
+ output Y,
input A
);
parameter [1:0] INIT = 2'h0;
- assign O = INIT >> A;
+ assign Y = INIT >> A;
endmodule
module CFG2 (
- output O,
+ output Y,
input A,
input B
);
parameter [3:0] INIT = 4'h0;
- assign O = INIT >> {B, A};
+ assign Y = INIT >> {B, A};
endmodule
module CFG3 (
- output O,
+ output Y,
input A,
input B,
input C
);
parameter [7:0] INIT = 8'h0;
- assign O = INIT >> {C, B, A};
+ assign Y = INIT >> {C, B, A};
endmodule
module CFG4 (
- output O,
+ output Y,
input A,
input B,
input C,
input D
);
parameter [15:0] INIT = 16'h0;
- assign O = INIT >> {D, C, B, A};
+ assign Y = INIT >> {D, C, B, A};
endmodule