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| author | Claire Xen <claire@clairexen.net> | 2022-02-11 16:03:12 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-02-11 16:03:12 +0100 |
| commit | 49545c73f7f5a5cf73d287fd371f2ff39311f621 (patch) | |
| tree | d0f20b8def36e551c6735d4fc6033aaa2633fe80 /techlibs/quicklogic/abc9_model.v | |
| parent | 90b40aa51f7d666792d4f0b1830ee75b81678a1f (diff) | |
| parent | e0165188669fcef2c5784c9916683889a2164e5d (diff) | |
| download | yosys-49545c73f7f5a5cf73d287fd371f2ff39311f621.tar.gz yosys-49545c73f7f5a5cf73d287fd371f2ff39311f621.tar.bz2 yosys-49545c73f7f5a5cf73d287fd371f2ff39311f621.zip | |
Merge branch 'master' into clk2ff-better-names
Diffstat (limited to 'techlibs/quicklogic/abc9_model.v')
| -rw-r--r-- | techlibs/quicklogic/abc9_model.v | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/techlibs/quicklogic/abc9_model.v b/techlibs/quicklogic/abc9_model.v new file mode 100644 index 000000000..06d4a2a56 --- /dev/null +++ b/techlibs/quicklogic/abc9_model.v @@ -0,0 +1,11 @@ +(* abc9_flop, lib_whitebox *) +module $__PP3_DFFEPC_SYNCONLY ( + output Q, + input D, + input CLK, + input EN, +); + + dffepc ff (.Q(Q), .D(D), .CLK(CLK), .EN(EN), .PRE(1'b0), .CLR(1'b0)); + +endmodule |