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author | William D. Jones <thor0505@comcast.net> | 2020-11-16 15:07:32 -0500 |
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committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2021-02-23 17:39:58 +0100 |
commit | 88c8f812602c25ef0a062002bede8fe737b6ac77 (patch) | |
tree | d5708ff20cb24d30a9a96dc36d9e0b3e91879efd /techlibs/machxo2/cells_map.v | |
parent | cc7d18d29a5314c6350b7378bc788f48f3925337 (diff) | |
download | yosys-88c8f812602c25ef0a062002bede8fe737b6ac77.tar.gz yosys-88c8f812602c25ef0a062002bede8fe737b6ac77.tar.bz2 yosys-88c8f812602c25ef0a062002bede8fe737b6ac77.zip |
machxo2: Create basic techlibs and synth_machxo2 pass.
Diffstat (limited to 'techlibs/machxo2/cells_map.v')
-rw-r--r-- | techlibs/machxo2/cells_map.v | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/techlibs/machxo2/cells_map.v b/techlibs/machxo2/cells_map.v new file mode 100644 index 000000000..0f21fc32b --- /dev/null +++ b/techlibs/machxo2/cells_map.v @@ -0,0 +1,23 @@ +module \$lut (A, Y); + parameter WIDTH = 0; + parameter LUT = 0; + input [WIDTH-1:0] A; + output Y; + + localparam rep = 1<<(4-WIDTH); + wire [3:0] I; + + generate + if(WIDTH == 2) begin + assign I = {1'b0, 1'b0, A[1], A[0]}; + end else if(WIDTH == 3) begin + assign I = {1'b0, A[2], A[1], A[0]}; + end else if(WIDTH == 4) begin + assign I = {A[3], A[2], A[1], A[0]}; + end + endgenerate + + LUT4 #(.INIT({rep{LUT}})) _TECHMAP_REPLACE_ (.A(I[0]), .B(I[1]), .C(I[2]), .D(I[3]), .F(Y)); +endmodule + +module \$_DFF_P_ (input D, C, output Q); FACADE_FF #(.CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .D(D), .Q(Q)); endmodule |