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author | whitequark <whitequark@whitequark.org> | 2020-06-18 23:34:52 +0000 |
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committer | whitequark <whitequark@whitequark.org> | 2020-06-18 23:34:52 +0000 |
commit | 7191dd16f9d486fbe107b2c24d1858c8f88329b3 (patch) | |
tree | 11a32e71b94bc030afc32d3f8d4c8f3d3ada1588 /techlibs/intel_alm | |
parent | dfde1cf1c540d5580d7bc7d24f9f59a004202d60 (diff) | |
download | yosys-7191dd16f9d486fbe107b2c24d1858c8f88329b3.tar.gz yosys-7191dd16f9d486fbe107b2c24d1858c8f88329b3.tar.bz2 yosys-7191dd16f9d486fbe107b2c24d1858c8f88329b3.zip |
Use C++11 final/override keywords.
Diffstat (limited to 'techlibs/intel_alm')
-rw-r--r-- | techlibs/intel_alm/synth_intel_alm.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc index 6508affc0..fabfc9003 100644 --- a/techlibs/intel_alm/synth_intel_alm.cc +++ b/techlibs/intel_alm/synth_intel_alm.cc @@ -29,7 +29,7 @@ PRIVATE_NAMESPACE_BEGIN struct SynthIntelALMPass : public ScriptPass { SynthIntelALMPass() : ScriptPass("synth_intel_alm", "synthesis for ALM-based Intel (Altera) FPGAs.") {} - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -74,7 +74,7 @@ struct SynthIntelALMPass : public ScriptPass { string top_opt, family_opt, bram_type, vout_file; bool flatten, quartus, nolutram, nobram; - void clear_flags() YS_OVERRIDE + void clear_flags() override { top_opt = "-auto-top"; family_opt = "cyclonev"; @@ -86,7 +86,7 @@ struct SynthIntelALMPass : public ScriptPass { nobram = false; } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { string run_from, run_to; clear_flags(); @@ -153,7 +153,7 @@ struct SynthIntelALMPass : public ScriptPass { log_pop(); } - void script() YS_OVERRIDE + void script() override { if (help_mode) { family_opt = "<family>"; |