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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-06-01 01:48:35 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-06-01 03:18:02 +0200 |
| commit | 6d5d8457883e5de8df58997d95373d3433b781bf (patch) | |
| tree | 39c7b75417a8266281ac90335f919f15ff63b26d /techlibs/intel_alm/synth_intel_alm.cc | |
| parent | 13b901bf1c5ac7d25ea061fc129d944ea0317150 (diff) | |
| download | yosys-6d5d8457883e5de8df58997d95373d3433b781bf.tar.gz yosys-6d5d8457883e5de8df58997d95373d3433b781bf.tar.bz2 yosys-6d5d8457883e5de8df58997d95373d3433b781bf.zip | |
kernel/mem: Recognize some deprecated memory port configs.
Transparency is meaningless for asynchronous ports, so we assume
transparent == false to simplify the code in this case. Likewise,
enable is meaningless, and we assume it is const-1. However,
turns out that nMigen emits the former, and Verilog frontend emits
the latter, so squash these issues when ingesting a $memrd cell.
Fixes #2811.
Diffstat (limited to 'techlibs/intel_alm/synth_intel_alm.cc')
0 files changed, 0 insertions, 0 deletions