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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-10-08 13:33:47 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-10-08 18:05:51 +0200 |
| commit | 7670a89e1fde7d0774695ab81031a90fafdf56b9 (patch) | |
| tree | 063e90c411b1e76e395460c27402a9a504b7f00d /techlibs/intel_alm/cyclonev | |
| parent | fd306b0520ac42323cbfacfa3a41e7a7a9379ec0 (diff) | |
| download | yosys-7670a89e1fde7d0774695ab81031a90fafdf56b9.tar.gz yosys-7670a89e1fde7d0774695ab81031a90fafdf56b9.tar.bz2 yosys-7670a89e1fde7d0774695ab81031a90fafdf56b9.zip | |
opt_clean: Better memory handling.
Previously, `$memwr` and `$meminit` cells were always preserved (along
with the memory itself). With this change, they are instead part of the
main cell mark-and-sweep pass: a memory (and its `$meminit` and `$memwr`
cells) is only preserved iff any associated `$memrd` cell needs to be
preserved.
Diffstat (limited to 'techlibs/intel_alm/cyclonev')
0 files changed, 0 insertions, 0 deletions