diff options
| author | Lofty <dan.ravensloft@gmail.com> | 2022-03-09 16:40:32 +0000 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2022-03-09 20:18:06 +0000 |
| commit | 9f7a55c99ff179e503397b5c9929de7ca97fd793 (patch) | |
| tree | 88d6e81cea45f30341a48a5cf25c7dc18c57ff9d /techlibs/intel_alm/common/quartus_rename.v | |
| parent | 4ccc2adbda523283997f273b0f182807ab07c0a9 (diff) | |
| download | yosys-9f7a55c99ff179e503397b5c9929de7ca97fd793.tar.gz yosys-9f7a55c99ff179e503397b5c9929de7ca97fd793.tar.bz2 yosys-9f7a55c99ff179e503397b5c9929de7ca97fd793.zip | |
intel_alm: M10K write-enable is negative-true
Diffstat (limited to 'techlibs/intel_alm/common/quartus_rename.v')
| -rw-r--r-- | techlibs/intel_alm/common/quartus_rename.v | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/techlibs/intel_alm/common/quartus_rename.v b/techlibs/intel_alm/common/quartus_rename.v index 5850f6907..217dc5de9 100644 --- a/techlibs/intel_alm/common/quartus_rename.v +++ b/techlibs/intel_alm/common/quartus_rename.v @@ -157,6 +157,11 @@ output [CFG_DBITS-1:0] B1DATA; // Much like the MLAB, the M10K has mem_init[01234] parameters which would let // you initialise the RAM cell via hex literals. If they were implemented. +// Since the MISTRAL_M10K block has an inverted write-enable (like the real hardware) +// but the Quartus primitive expects a normal write-enable, we add an inverter. +wire A1EN_N; +NOT wren_inv (.IN(A1EN), .OUT(A1EN_N)); + `RAM_BLOCK #( .operation_mode("dual_port"), .logical_ram_name(_TECHMAP_CELLNAME_), @@ -176,10 +181,10 @@ output [CFG_DBITS-1:0] B1DATA; .port_b_first_bit_number(0), .port_b_address_clock("clock0"), .port_b_read_enable_clock("clock0") -) _TECHMAP_REPLACE_ ( +) ram_block ( .portaaddr(A1ADDR), .portadatain(A1DATA), - .portawe(A1EN), + .portawe(A1EN_N), .portbaddr(B1ADDR), .portbdataout(B1DATA), .portbre(B1EN), |