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| author | Claire Wolf <claire@symbioticeda.com> | 2020-05-01 17:26:34 +0200 |
|---|---|---|
| committer | Claire Wolf <claire@symbioticeda.com> | 2020-05-02 11:21:01 +0200 |
| commit | c3e5a070eac753cfd54058f7e186bad0742301ed (patch) | |
| tree | c3ddd6897e36eb9623c3eb213ad9a68d4a1fbfed /techlibs/intel_alm/common/mem_sim.v | |
| parent | f38d76efbfa456533837d614822d2b89302386f9 (diff) | |
| download | yosys-c3e5a070eac753cfd54058f7e186bad0742301ed.tar.gz yosys-c3e5a070eac753cfd54058f7e186bad0742301ed.tar.bz2 yosys-c3e5a070eac753cfd54058f7e186bad0742301ed.zip | |
Add plusargs for output files in test_autotb output
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
Diffstat (limited to 'techlibs/intel_alm/common/mem_sim.v')
0 files changed, 0 insertions, 0 deletions