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| author | Dan Ravensloft <dan.ravensloft@gmail.com> | 2020-07-21 13:58:38 +0100 |
|---|---|---|
| committer | Dan Ravensloft <dan.ravensloft@gmail.com> | 2020-07-23 11:57:07 +0100 |
| commit | 4d9d90079c6e069fcba7ce04e8005285f4f237fe (patch) | |
| tree | a9f6ef195c0fe55d298095f36af349ae23a7da3e /techlibs/intel_alm/common/mem_sim.v | |
| parent | eed05953f820439178b2138cef7d53d50528354a (diff) | |
| download | yosys-4d9d90079c6e069fcba7ce04e8005285f4f237fe.tar.gz yosys-4d9d90079c6e069fcba7ce04e8005285f4f237fe.tar.bz2 yosys-4d9d90079c6e069fcba7ce04e8005285f4f237fe.zip | |
intel_alm: add additional ABC9 timings
Diffstat (limited to 'techlibs/intel_alm/common/mem_sim.v')
| -rw-r--r-- | techlibs/intel_alm/common/mem_sim.v | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/techlibs/intel_alm/common/mem_sim.v b/techlibs/intel_alm/common/mem_sim.v index f6f9ecb02..b0e1763db 100644 --- a/techlibs/intel_alm/common/mem_sim.v +++ b/techlibs/intel_alm/common/mem_sim.v @@ -54,12 +54,17 @@ module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1 reg [31:0] mem = 32'b0; -// TODO +// TODO: Cyclone 10 GX timings; the below timings are for Cyclone V specify - $setup(A1ADDR, posedge CLK1, 0); - $setup(A1DATA, posedge CLK1, 0); + $setup(A1ADDR, posedge CLK1, 86); + $setup(A1DATA, posedge CLK1, 86); + $setup(A1EN, posedge CLK1, 86); - (B1ADDR *> B1DATA) = 0; + (B1ADDR[0] => B1DATA) = 487; + (B1ADDR[1] => B1DATA) = 475; + (B1ADDR[2] => B1DATA) = 382; + (B1ADDR[3] => B1DATA) = 284; + (B1ADDR[4] => B1DATA) = 96; endspecify always @(posedge CLK1) |