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| author | Dan Ravensloft <dan.ravensloft@gmail.com> | 2019-11-19 10:19:00 +0000 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-04-15 11:40:41 +0200 |
| commit | 2e37e62e6b926ca1712b1636ef720748e382dc97 (patch) | |
| tree | 25936d690dff24f0cddcc5dbbfe68aea74500994 /techlibs/intel_alm/common/bram_m20k.txt | |
| parent | 4c52691a58a469a525401bbc83c65f262b2a5504 (diff) | |
| download | yosys-2e37e62e6b926ca1712b1636ef720748e382dc97.tar.gz yosys-2e37e62e6b926ca1712b1636ef720748e382dc97.tar.bz2 yosys-2e37e62e6b926ca1712b1636ef720748e382dc97.zip | |
synth_intel_alm: alternative synthesis for Intel FPGAs
By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.
This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
Diffstat (limited to 'techlibs/intel_alm/common/bram_m20k.txt')
| -rw-r--r-- | techlibs/intel_alm/common/bram_m20k.txt | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/techlibs/intel_alm/common/bram_m20k.txt b/techlibs/intel_alm/common/bram_m20k.txt new file mode 100644 index 000000000..b4c5a5372 --- /dev/null +++ b/techlibs/intel_alm/common/bram_m20k.txt @@ -0,0 +1,33 @@ +bram __MISTRAL_M20K_SDP + init 1 # TODO: Re-enable when I figure out how BRAM init works + abits 14 @D16384x1 + dbits 1 @D16384x1 + abits 13 @D8192x2 + dbits 2 @D8192x2 + abits 12 @D4096x4 @D4096x5 + dbits 4 @D4096x4 + dbits 5 @D4096x5 + abits 11 @D2048x8 @D2048x10 + dbits 8 @D2048x8 + dbits 10 @D2048x10 + abits 10 @D1024x16 @D1024x20 + dbits 16 @D1024x16 + dbits 20 @D1024x20 + abits 9 @D512x32 @D512x40 + dbits 32 @D512x32 + dbits 40 @D512x40 + groups 2 + ports 1 1 + wrmode 1 0 + # read enable; write enable + byte enables (only for multiples of 8) + enable 1 1 + transp 0 0 + clocks 1 1 + clkpol 1 1 +endbram + + +match __MISTRAL_M20K_SDP + min efficiency 5 + make_transp +endmatch |