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| author | Staf Verhaegen <staf@stafverhaegen.be> | 2018-01-03 20:36:22 +0000 |
|---|---|---|
| committer | Staf Verhaegen <staf@stafverhaegen.be> | 2018-01-03 21:37:17 +0000 |
| commit | 92eb841f0a506ce776d511ec443769f5bcc2961f (patch) | |
| tree | f38b5b71f3beb438d3839ca06eb56e953853d9a9 /techlibs/intel | |
| parent | 9804ebedbfd7db66849874bd11b167deb1bfed18 (diff) | |
| download | yosys-92eb841f0a506ce776d511ec443769f5bcc2961f.tar.gz yosys-92eb841f0a506ce776d511ec443769f5bcc2961f.tar.bz2 yosys-92eb841f0a506ce776d511ec443769f5bcc2961f.zip | |
Value of properties can be expression.
Example found in the 2007.03 Liberty Reference Manual that was also found
in the wild:
input_voltage(CMOS) {
vil : 0.3 * VDD ;
vih : 0.7 * VDD ;
vimin : -0.5 ;
vimax : VDD + 0.5 ;
}
Current implementation just parses the expression but no interpretation is done.
Diffstat (limited to 'techlibs/intel')
0 files changed, 0 insertions, 0 deletions