diff options
| author | Jim Lawson <ucbjrl@berkeley.edu> | 2019-03-01 10:31:26 -0800 |
|---|---|---|
| committer | Jim Lawson <ucbjrl@berkeley.edu> | 2019-03-01 10:31:26 -0800 |
| commit | 4cce7f6967313772207448569635e6e5c6bc44ce (patch) | |
| tree | 8132003faa377602a74f5ac16f9899f9b17eb8c3 /techlibs/intel/cyclonev | |
| parent | 81abb2517c3d6e8fd2b31ff6d9d019d956a6bc14 (diff) | |
| parent | 60e3c38054f10251021fa2f504ad2424da33aa1d (diff) | |
| download | yosys-4cce7f6967313772207448569635e6e5c6bc44ce.tar.gz yosys-4cce7f6967313772207448569635e6e5c6bc44ce.tar.bz2 yosys-4cce7f6967313772207448569635e6e5c6bc44ce.zip | |
Merge remote-tracking branch 'upstream/master'
Diffstat (limited to 'techlibs/intel/cyclonev')
| -rw-r--r-- | techlibs/intel/cyclonev/cells_map.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/intel/cyclonev/cells_map.v b/techlibs/intel/cyclonev/cells_map.v index bd60d4e17..f8d142bc9 100644 --- a/techlibs/intel/cyclonev/cells_map.v +++ b/techlibs/intel/cyclonev/cells_map.v @@ -76,7 +76,7 @@ module \$lut (A, Y); wire VCC; wire GND; assign {VCC,GND} = {1'b1,1'b0}; - + generate if (WIDTH == 1) begin assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function @@ -151,7 +151,7 @@ module \$lut (A, Y); TODO: There's not a just 7-input function on Cyclone V, see the following note: **Extended LUT Mode** Use extended LUT mode to implement a specific set of 7-input functions. The set must - be a 2-to-1 multiplexer fed by two arbitrary 5-input functions sharing four inputs. + be a 2-to-1 multiplexer fed by two arbitrary 5-input functions sharing four inputs. [source](Device Interfaces and Integration Basics for Cyclone V Devices). end*/ else |