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| author | Aman Goel <amangoel@umich.edu> | 2019-09-27 12:30:27 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-09-27 12:30:27 -0400 |
| commit | cb0dc6e68b9432edc9c30c153954be53c8576911 (patch) | |
| tree | c137f970f949117d04632158d73bfe1f9c146e6f /techlibs/intel/cycloneive | |
| parent | 4d343fc1cdafe469484846051680ca0b1f948549 (diff) | |
| parent | 4b15cf5f76e2226bbce1a73d1e0ff54fbf093fe8 (diff) | |
| download | yosys-cb0dc6e68b9432edc9c30c153954be53c8576911.tar.gz yosys-cb0dc6e68b9432edc9c30c153954be53c8576911.tar.bz2 yosys-cb0dc6e68b9432edc9c30c153954be53c8576911.zip | |
Merge pull request #7 from YosysHQ/master
Syncing with official repo
Diffstat (limited to 'techlibs/intel/cycloneive')
| -rw-r--r-- | techlibs/intel/cycloneive/arith_map.v | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/techlibs/intel/cycloneive/arith_map.v b/techlibs/intel/cycloneive/arith_map.v index b3a11272b..49e36aa25 100644 --- a/techlibs/intel/cycloneive/arith_map.v +++ b/techlibs/intel/cycloneive/arith_map.v @@ -32,7 +32,7 @@ module fa wire VCC; assign VCC = 1'b1; - + cycloneiv_lcell_comb gen_sum_0 (.combout(sum_x), .dataa(a_c), .datab(b_c), @@ -40,7 +40,7 @@ module fa .datad(VCC)); defparam syn__05_.lut_mask = 16'b1001011010010110; defparam syn__05_.sum_lutc_input = "datac"; - + cycloneiv_lcell_comb gen_cout_0 (.combout(cout_t), .dataa(cin_c), .datab(b_c), @@ -48,11 +48,11 @@ module fa .datad(VCC)); defparam syn__06_.lut_mask = 16'b1110000011100000; defparam syn__06_.sum_lutc_input = "datac"; - + endmodule // fa module f_stage(); - + endmodule // f_stage module f_end(); @@ -88,7 +88,7 @@ module _80_cycloneive_alu (A, B, CI, BI, X, Y, CO); .cin_c(C[0]), .cout_t(C0[1]), .sum_x(Y[0])); - + genvar i; generate for (i = 1; i < Y_WIDTH; i = i + 1) begin:slice cycloneive_lcell_comb #(.lut_mask(16'b0101_1010_0101_0000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(CO[i]), .dataa(BB[i]), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[i])); |