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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-22 18:18:50 +0200 |
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| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-25 02:07:25 +0200 |
| commit | 69bf5c81c7cf65ccb8bd035eb45137e31a68ae86 (patch) | |
| tree | c27924c314fde30979aa0b91f8b179e71c15dd04 /techlibs/intel/cycloneive | |
| parent | 35ee774ea8eac9b745f93641a192341fe559fa6f (diff) | |
| download | yosys-69bf5c81c7cf65ccb8bd035eb45137e31a68ae86.tar.gz yosys-69bf5c81c7cf65ccb8bd035eb45137e31a68ae86.tar.bz2 yosys-69bf5c81c7cf65ccb8bd035eb45137e31a68ae86.zip | |
Reject wide ports in some passes that will never support them.
Diffstat (limited to 'techlibs/intel/cycloneive')
0 files changed, 0 insertions, 0 deletions