diff options
| author | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2017-10-04 17:01:30 -0700 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-10-05 16:23:49 +0200 |
| commit | 50bcd9a728ff89f220873b3345c4e18a65c4a37f (patch) | |
| tree | ff7b306d49b46ec25b7bfac26ca9ace82302a3f0 /techlibs/intel/cycloneive/arith_map.v | |
| parent | fc3378916dbaf46018a99571ef190189088c225c (diff) | |
| download | yosys-50bcd9a728ff89f220873b3345c4e18a65c4a37f.tar.gz yosys-50bcd9a728ff89f220873b3345c4e18a65c4a37f.tar.bz2 yosys-50bcd9a728ff89f220873b3345c4e18a65c4a37f.zip | |
Clean whitespace and permissions in techlibs/intel
Diffstat (limited to 'techlibs/intel/cycloneive/arith_map.v')
| -rw-r--r--[-rwxr-xr-x] | techlibs/intel/cycloneive/arith_map.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/intel/cycloneive/arith_map.v b/techlibs/intel/cycloneive/arith_map.v index 3eaec3715..634cec789 100755..100644 --- a/techlibs/intel/cycloneive/arith_map.v +++ b/techlibs/intel/cycloneive/arith_map.v @@ -40,7 +40,7 @@ module _80_cycloneive_alu (A, B, CI, BI, X, Y, CO); wire [Y_WIDTH-1:0] AA = A_buf; wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; wire [Y_WIDTH:0] C = {CO, CI}; - + cycloneive_lcell_comb #(.lut_mask(16'b0110_0110_1000_1000), .sum_lutc_input("cin")) carry_start (.cout(CO[0]), .dataa(BB[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1)); genvar i; generate for (i = 1; i < Y_WIDTH; i = i + 1) begin:slice @@ -48,5 +48,5 @@ module _80_cycloneive_alu (A, B, CI, BI, X, Y, CO); end endgenerate assign X = AA ^ BB; - + endmodule |