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authordh73 <dh73_fpga@qq.com>2017-11-08 22:45:21 -0600
committerdh73 <dh73_fpga@qq.com>2017-11-08 22:45:21 -0600
commit3fd1d61e2aa65bfc88de691071a3295888ed2aa3 (patch)
tree04ebf8a6b55de9991760af4206f6c064e4de7278 /techlibs/intel/Makefile.inc
parentcf8cc50bf51c2fa36a3189e131a7e7fe0807ae8f (diff)
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Initial Cyclone 10 support
Diffstat (limited to 'techlibs/intel/Makefile.inc')
-rw-r--r--techlibs/intel/Makefile.inc2
1 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/intel/Makefile.inc b/techlibs/intel/Makefile.inc
index 429d23677..ec7cea379 100644
--- a/techlibs/intel/Makefile.inc
+++ b/techlibs/intel/Makefile.inc
@@ -8,11 +8,13 @@ $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map.
$(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/cells_sim.v))
$(eval $(call add_share_file,share/intel/a10gx,techlibs/intel/a10gx/cells_sim.v))
$(eval $(call add_share_file,share/intel/cyclonev,techlibs/intel/cyclonev/cells_sim.v))
+$(eval $(call add_share_file,share/intel/cyclone10,techlibs/intel/cyclone10/cells_sim.v))
$(eval $(call add_share_file,share/intel/cycloneiv,techlibs/intel/cycloneiv/cells_sim.v))
$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/cells_sim.v))
$(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/cells_map.v))
$(eval $(call add_share_file,share/intel/a10gx,techlibs/intel/a10gx/cells_map.v))
$(eval $(call add_share_file,share/intel/cyclonev,techlibs/intel/cyclonev/cells_map.v))
+$(eval $(call add_share_file,share/intel/cyclone10,techlibs/intel/cyclone10/cells_map.v))
$(eval $(call add_share_file,share/intel/cycloneiv,techlibs/intel/cycloneiv/cells_map.v))
$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/cells_map.v))
#$(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/arith_map.v))