Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"

6 files changed, 150 insertions, 32 deletions

diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index 76a89b107..d258d5a5d 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -4,6 +4,7 @@ OBJS += techlibs/ice40/ice40_braminit.o
 OBJS += techlibs/ice40/ice40_ffssr.o
 OBJS += techlibs/ice40/ice40_ffinit.o
 OBJS += techlibs/ice40/ice40_opt.o
+OBJS += techlibs/ice40/ice40_unlut.o
 
 GENFILES += techlibs/ice40/brams_init1.vh
 GENFILES += techlibs/ice40/brams_init2.vh
diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v
index 26b24db9e..fe83a8e38 100644
--- a/techlibs/ice40/arith_map.v
+++ b/techlibs/ice40/arith_map.v
@@ -44,21 +44,35 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
 
 	genvar i;
 	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
-		\$__ICE40_CARRY_WRAPPER #(
-			//    A[0]: 1010 1010 1010 1010
-			//    A[1]: 1100 1100 1100 1100
-			//    A[2]: 1111 0000 1111 0000
-			//    A[3]: 1111 1111 0000 0000
-			.LUT(16'b 0110_1001_1001_0110)
-		) fadd (
+`ifdef _ABC
+		\$__ICE40_FULL_ADDER carry (
 			.A(AA[i]),
 			.B(BB[i]),
 			.CI(C[i]),
+			.CO(CO[i]),
+			.O(Y[i])
+		);
+`else
+		SB_CARRY carry (
+			.I0(AA[i]),
+			.I1(BB[i]),
+			.CI(C[i]),
+			.CO(CO[i])
+		);
+		SB_LUT4 #(
+			//         I0: 1010 1010 1010 1010
+			//         I1: 1100 1100 1100 1100
+			//         I2: 1111 0000 1111 0000
+			//         I3: 1111 1111 0000 0000
+			.LUT_INIT(16'b 0110_1001_1001_0110)
+		) adder (
 			.I0(1'b0),
+			.I1(AA[i]),
+			.I2(BB[i]),
 			.I3(C[i]),
-			.CO(CO[i]),
 			.O(Y[i])
 		);
+`endif
 	end endgenerate
 
 	assign X = AA ^ BB;
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index 0c10c9ac4..b4b831165 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -62,21 +62,26 @@ module \$lut (A, Y);
 endmodule
 `endif
 
-`ifndef NO_ADDER
-module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3);
-  parameter LUT = 0;
+`ifdef _ABC
+module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
   SB_CARRY carry (
     .I0(A),
     .I1(B),
     .CI(CI),
     .CO(CO)
   );
-  \$lut #(
-    .WIDTH(4),
-    .LUT(LUT)
-  ) lut (
-    .A({I3,B,A,I0}),
-    .Y(O)
+  SB_LUT4 #(
+    //         I0: 1010 1010 1010 1010
+    //         I1: 1100 1100 1100 1100
+    //         I2: 1111 0000 1111 0000
+    //         I3: 1111 1111 0000 0000
+    .LUT_INIT(16'b 0110_1001_1001_0110)
+  ) adder (
+    .I0(1'b0),
+    .I1(A),
+    .I2(B),
+    .I3(CI),
+    .O(O)
   );
 endmodule
 `endif
diff --git a/techlibs/ice40/ice40_unlut.cc b/techlibs/ice40/ice40_unlut.cc
new file mode 100644
index 000000000..f3f70ac1f
--- /dev/null
+++ b/techlibs/ice40/ice40_unlut.cc
@@ -0,0 +1,106 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+#include <stdlib.h>
+#include <stdio.h>
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+static SigBit get_bit_or_zero(const SigSpec &sig)
+{
+	if (GetSize(sig) == 0)
+		return State::S0;
+	return sig[0];
+}
+
+static void run_ice40_unlut(Module *module)
+{
+	SigMap sigmap(module);
+
+	for (auto cell : module->selected_cells())
+	{
+		if (cell->type == "\\SB_LUT4")
+		{
+			SigSpec inbits;
+
+			inbits.append(get_bit_or_zero(cell->getPort("\\I0")));
+			inbits.append(get_bit_or_zero(cell->getPort("\\I1")));
+			inbits.append(get_bit_or_zero(cell->getPort("\\I2")));
+			inbits.append(get_bit_or_zero(cell->getPort("\\I3")));
+			sigmap.apply(inbits);
+
+			log("Mapping SB_LUT4 cell %s.%s to $lut.\n", log_id(module), log_id(cell));
+
+			cell->type ="$lut";
+			cell->setParam("\\WIDTH", 4);
+			cell->setParam("\\LUT", cell->getParam("\\LUT_INIT"));
+			cell->unsetParam("\\LUT_INIT");
+
+			cell->setPort("\\A", SigSpec({
+				get_bit_or_zero(cell->getPort("\\I0")),
+				get_bit_or_zero(cell->getPort("\\I1")),
+				get_bit_or_zero(cell->getPort("\\I2")),
+				get_bit_or_zero(cell->getPort("\\I3"))
+			}));
+			cell->setPort("\\Y", cell->getPort("\\O")[0]);
+			cell->unsetPort("\\I0");
+			cell->unsetPort("\\I1");
+			cell->unsetPort("\\I2");
+			cell->unsetPort("\\I3");
+			cell->unsetPort("\\O");
+
+			cell->check();
+		}
+	}
+}
+
+struct Ice40UnlutPass : public Pass {
+	Ice40UnlutPass() : Pass("ice40_unlut", "iCE40: transform SB_LUT4 cells to $lut cells") { }
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    ice40_unlut [options] [selection]\n");
+		log("\n");
+		log("This command transforms all SB_LUT4 cells to generic $lut cells.\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		log_header(design, "Executing ICE40_UNLUT pass (convert SB_LUT4 to $lut).\n");
+		log_push();
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			// if (args[argidx] == "-???") {
+			//  continue;
+			// }
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		for (auto module : design->selected_modules())
+			run_ice40_unlut(module);
+	}
+} Ice40UnlutPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index c6de81bd9..dc04eed67 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -238,7 +238,7 @@ struct SynthIce40Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -icells -lib +/ice40/cells_sim.v");
+			run("read_verilog -icells -lib -D_ABC +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 			run("proc");
 		}
@@ -293,10 +293,8 @@ struct SynthIce40Pass : public ScriptPass
 		{
 			if (nocarry)
 				run("techmap");
-			else {
-				run("ice40_wrapcarry");
-				run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
-			}
+			else
+				run("techmap -map +/techmap.v -map +/ice40/arith_map.v" + std::string(abc == "abc9" ? " -D _ABC" : ""));
 			if (retime || help_mode)
 				run(abc + " -dff", "(only if -retime)");
 			run("ice40_opt");
@@ -311,7 +309,7 @@ struct SynthIce40Pass : public ScriptPass
 				run("opt_merge");
 				run(stringf("dff2dffe -unmap-mince %d", min_ce_use));
 			}
-			run("techmap -D NO_LUT -D NO_ADDER -map +/ice40/cells_map.v");
+			run("techmap -D NO_LUT -map +/ice40/cells_map.v");
 			run("opt_expr -mux_undef");
 			run("simplemap");
 			run("ice40_ffinit");
@@ -340,12 +338,13 @@ struct SynthIce40Pass : public ScriptPass
 					else
 						wire_delay = 250;
 					run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
+					run("techmap -D NO_LUT -D _ABC -map +/ice40/cells_map.v");
 				}
 				else
 					run(abc + " -dress -lut 4", "(skip if -noabc)");
 			}
-			run("techmap -D NO_LUT -map +/ice40/cells_map.v");
 			run("clean");
+			run("ice40_unlut");
 			run("opt_lut -dlogic SB_CARRY:I0=2:I1=1:CI=0");
 		}
 
diff --git a/techlibs/ice40/tests/test_arith.ys b/techlibs/ice40/tests/test_arith.ys
index ddb80b700..160c767fb 100644
--- a/techlibs/ice40/tests/test_arith.ys
+++ b/techlibs/ice40/tests/test_arith.ys
@@ -1,5 +1,6 @@
 read_verilog test_arith.v
 synth_ice40
+techmap -map ../cells_sim.v
 rename test gate
 
 read_verilog test_arith.v
@@ -7,11 +8,3 @@ rename test gold
 
 miter -equiv -flatten -make_outputs gold gate miter
 sat -verify -prove trigger 0 -show-ports miter
-
-synth_ice40 -top gate
-
-read_verilog test_arith.v
-rename test gold
-
-miter -equiv -flatten -make_outputs gold gate miter
-sat -verify -prove trigger 0 -show-ports miter