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| author | Clifford Wolf <clifford@clifford.at> | 2016-06-30 09:58:13 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-06-30 09:58:13 +0200 |
| commit | df5ebfa0a0fc6d060caaa21b74a2f1a7b4ba0f86 (patch) | |
| tree | d1628972c2deeaf2c0f44c276007fd31da4c6e6e /techlibs/ice40 | |
| parent | 7cddab0788cadc220ffa098c4ac037362ad6948e (diff) | |
| download | yosys-df5ebfa0a0fc6d060caaa21b74a2f1a7b4ba0f86.tar.gz yosys-df5ebfa0a0fc6d060caaa21b74a2f1a7b4ba0f86.tar.bz2 yosys-df5ebfa0a0fc6d060caaa21b74a2f1a7b4ba0f86.zip | |
Improved ice40_ffinit error reporting
Diffstat (limited to 'techlibs/ice40')
| -rw-r--r-- | techlibs/ice40/ice40_ffinit.cc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/techlibs/ice40/ice40_ffinit.cc b/techlibs/ice40/ice40_ffinit.cc index db2100381..8a2c30d6a 100644 --- a/techlibs/ice40/ice40_ffinit.cc +++ b/techlibs/ice40/ice40_ffinit.cc @@ -57,6 +57,7 @@ struct Ice40FfinitPass : public Pass { SigMap sigmap(module); pool<Wire*> init_wires; dict<SigBit, State> initbits; + dict<SigBit, SigBit> initbit_to_wire; pool<SigBit> handled_initbits; for (auto wire : module->selected_wires()) @@ -78,11 +79,14 @@ struct Ice40FfinitPass : public Pass { if (initbits.count(bit)) { if (initbits.at(bit) != val) - log_error("Conflicting init values for signal %s.\n", log_signal(bit)); + log_error("Conflicting init values for signal %s (%s = %s, %s = %s).\n", + log_signal(bit), log_signal(SigBit(wire, i)), log_signal(val), + log_signal(initbit_to_wire[bit]), log_signal(initbits.at(bit))); continue; } initbits[bit] = val; + initbit_to_wire[bit] = SigBit(wire, i); } } |