Merge branch 'master' into SergeyDegtyar/anlogic

4 files changed, 222 insertions, 24 deletions

diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index 76a89b107..92a9956ea 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -27,6 +27,7 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/dsp_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.box))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.lut))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_lp.box))
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 2a7487f6b..8e5e0358e 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -2,6 +2,10 @@
 `define SB_DFF_REG reg Q = 0
 // `define SB_DFF_REG reg Q
 
+`define ABC_ARRIVAL_HX(TIME) `ifdef ICE40_HX (* abc_arrival=TIME *) `endif
+`define ABC_ARRIVAL_LP(TIME) `ifdef ICE40_LP (* abc_arrival=TIME *) `endif
+`define ABC_ARRIVAL_U(TIME)  `ifdef ICE40_U (* abc_arrival=TIME *) `endif
+
 // SiliconBlue IO Cells
 
 module SB_IO (
@@ -169,20 +173,42 @@ module \$__ICE40_CARRY_WRAPPER (
 	);
 endmodule
 
+// Max delay from: https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+//                 https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
+//                 https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
+
 // Positive Edge SiliconBlue FF Cells
 
-module SB_DFF (output `SB_DFF_REG, input C, D);
+module SB_DFF (
+	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
+	output `SB_DFF_REG,
+	input C, D
+);
 	always @(posedge C)
 		Q <= D;
 endmodule
 
-module SB_DFFE (output `SB_DFF_REG, input C, E, D);
+module SB_DFFE (
+	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
+	output `SB_DFF_REG,
+	input C, E, D
+);
 	always @(posedge C)
 		if (E)
 			Q <= D;
 endmodule
 
-module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFSR (
+	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
+	output `SB_DFF_REG,
+	input C, R, D
+);
 	always @(posedge C)
 		if (R)
 			Q <= 0;
@@ -190,7 +216,13 @@ module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFR (
+	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
+	output `SB_DFF_REG,
+	input C, R, D
+);
 	always @(posedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -198,7 +230,13 @@ module SB_DFFR (output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFSS (
+	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
+	output `SB_DFF_REG,
+	input C, S, D
+);
 	always @(posedge C)
 		if (S)
 			Q <= 1;
@@ -206,7 +244,13 @@ module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFS (
+	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
+	output `SB_DFF_REG,
+	input C, S, D
+);
 	always @(posedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -214,7 +258,13 @@ module SB_DFFS (output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFESR (
+	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
+	output `SB_DFF_REG,
+	input C, E, R, D
+);
 	always @(posedge C)
 		if (E) begin
 			if (R)
@@ -224,7 +274,13 @@ module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
 		end
 endmodule
 
-module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFER (
+	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
+	output `SB_DFF_REG,
+	input C, E, R, D
+);
 	always @(posedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -232,7 +288,13 @@ module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFESS (
+	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
+	output `SB_DFF_REG,
+	input C, E, S, D
+);
 	always @(posedge C)
 		if (E) begin
 			if (S)
@@ -242,7 +304,13 @@ module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
 		end
 endmodule
 
-module SB_DFFES (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFES (
+	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
+	output `SB_DFF_REG,
+	input C, E, S, D
+);
 	always @(posedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -252,18 +320,36 @@ endmodule
 
 // Negative Edge SiliconBlue FF Cells
 
-module SB_DFFN (output `SB_DFF_REG, input C, D);
+module SB_DFFN (
+	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
+	output `SB_DFF_REG,
+	input C, D
+);
 	always @(negedge C)
 		Q <= D;
 endmodule
 
-module SB_DFFNE (output `SB_DFF_REG, input C, E, D);
+module SB_DFFNE (
+	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
+	output `SB_DFF_REG,
+	input C, E, D
+);
 	always @(negedge C)
 		if (E)
 			Q <= D;
 endmodule
 
-module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFNSR (
+	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
+	output `SB_DFF_REG,
+	input C, R, D
+);
 	always @(negedge C)
 		if (R)
 			Q <= 0;
@@ -271,7 +357,13 @@ module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFNR (
+	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
+	output `SB_DFF_REG,
+	input C, R, D
+);
 	always @(negedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -279,7 +371,13 @@ module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFNSS (
+	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
+	output `SB_DFF_REG,
+	input C, S, D
+);
 	always @(negedge C)
 		if (S)
 			Q <= 1;
@@ -287,7 +385,13 @@ module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFNS (
+	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
+	output `SB_DFF_REG,
+	input C, S, D
+);
 	always @(negedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -295,7 +399,13 @@ module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFNESR (
+	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
+	output `SB_DFF_REG,
+	input C, E, R, D
+);
 	always @(negedge C)
 		if (E) begin
 			if (R)
@@ -305,7 +415,13 @@ module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
 		end
 endmodule
 
-module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFNER (
+	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
+	output `SB_DFF_REG,
+	input C, E, R, D
+);
 	always @(negedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -313,7 +429,13 @@ module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFNESS (
+	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
+	output `SB_DFF_REG,
+	input C, E, S, D
+);
 	always @(negedge C)
 		if (E) begin
 			if (S)
@@ -323,7 +445,13 @@ module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
 		end
 endmodule
 
-module SB_DFFNES (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFNES (
+	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
+	output `SB_DFF_REG,
+	input C, E, S, D
+);
 	always @(negedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -334,6 +462,9 @@ endmodule
 // SiliconBlue RAM Cells
 
 module SB_RAM40_4K (
+	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+	`ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -502,6 +633,9 @@ module SB_RAM40_4K (
 endmodule
 
 module SB_RAM40_4KNR (
+	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+	`ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -567,6 +701,9 @@ module SB_RAM40_4KNR (
 endmodule
 
 module SB_RAM40_4KNW (
+	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+	`ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -632,6 +769,9 @@ module SB_RAM40_4KNW (
 endmodule
 
 module SB_RAM40_4KNRNW (
+	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+	`ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -700,7 +840,12 @@ endmodule
 
 module ICESTORM_LC (
 	input I0, I1, I2, I3, CIN, CLK, CEN, SR,
-	output LO, O, COUT
+	output LO,
+	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
+	output O,
+	output COUT
 );
 	parameter [15:0] LUT_INIT = 0;
 
@@ -1300,6 +1445,7 @@ module SB_MAC16 (
 	input ADDSUBTOP, ADDSUBBOT,
 	input OHOLDTOP, OHOLDBOT,
 	input CI, ACCUMCI, SIGNEXTIN,
+	//`ABC_ARRIVAL_U(1984)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [31:0] O,
 	output CO, ACCUMCO, SIGNEXTOUT
 );
diff --git a/techlibs/ice40/dsp_map.v b/techlibs/ice40/dsp_map.v
new file mode 100644
index 000000000..06fa73956
--- /dev/null
+++ b/techlibs/ice40/dsp_map.v
@@ -0,0 +1,34 @@
+module \$__MUL16X16 (input [15:0] A, input [15:0] B, output [31:0] Y);
+	parameter A_SIGNED = 0;
+	parameter B_SIGNED = 0;
+	parameter A_WIDTH = 0;
+	parameter B_WIDTH = 0;
+	parameter Y_WIDTH = 0;
+
+	SB_MAC16 #(
+		.NEG_TRIGGER(1'b0),
+		.C_REG(1'b0),
+		.A_REG(1'b0),
+		.B_REG(1'b0),
+		.D_REG(1'b0),
+		.TOP_8x8_MULT_REG(1'b0),
+		.BOT_8x8_MULT_REG(1'b0),
+		.PIPELINE_16x16_MULT_REG1(1'b0),
+		.PIPELINE_16x16_MULT_REG2(1'b0),
+		.TOPOUTPUT_SELECT(2'b11),
+		.TOPADDSUB_LOWERINPUT(2'b0),
+		.TOPADDSUB_UPPERINPUT(1'b0),
+		.TOPADDSUB_CARRYSELECT(2'b0),
+		.BOTOUTPUT_SELECT(2'b11),
+		.BOTADDSUB_LOWERINPUT(2'b0),
+		.BOTADDSUB_UPPERINPUT(1'b0),
+		.BOTADDSUB_CARRYSELECT(2'b0),
+		.MODE_8x8(1'b0),
+		.A_SIGNED(A_SIGNED),
+		.B_SIGNED(B_SIGNED)
+	) _TECHMAP_REPLACE_ (
+		.A(A),
+		.B(B),
+		.O(Y),
+	);
+endmodule
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index c6de81bd9..841f10244 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -238,7 +238,14 @@ struct SynthIce40Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -icells -lib +/ice40/cells_sim.v");
+			std::string define;
+			if (device_opt == "lp")
+				define = "-D ICE40_LP";
+			else if (device_opt == "u")
+				define = "-D ICE40_U";
+			else
+				define = "-D ICE40_HX";
+			run("read_verilog -icells " + define + " -lib +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 			run("proc");
 		}
@@ -265,8 +272,18 @@ struct SynthIce40Pass : public ScriptPass
 			run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
 			run("opt_expr");
 			run("opt_clean");
-			if (help_mode || dsp)
-				run("ice40_dsp", "(if -dsp)");
+			if (help_mode || dsp) {
+				run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 "
+						"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 "
+						"-D DSP_NAME=$__MUL16X16", "(if -dsp)");
+				run("select a:mul2dsp", "              (if -dsp)");
+				run("setattr -unset mul2dsp", "        (if -dsp)");
+				run("opt_expr -fine", "                (if -dsp)");
+				run("wreduce", "                       (if -dsp)");
+				run("select -clear", "                 (if -dsp)");
+				run("ice40_dsp", "                     (if -dsp)");
+				run("chtype -set $mul t:$__soft_mul", "(if -dsp)");
+			}
 			run("alumacc");
 			run("opt");
 			run("fsm");