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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-12 00:51:37 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-12 00:51:37 -0700 |
| commit | c6e16e1334dcbd8bb556ab566130cc7936f06a69 (patch) | |
| tree | aa39137aaa6b28f72879b83fce98810152233ce6 /techlibs/ice40 | |
| parent | fc3d74616f284eaccdc7d105cd77572953602d7f (diff) | |
| download | yosys-c6e16e1334dcbd8bb556ab566130cc7936f06a69.tar.gz yosys-c6e16e1334dcbd8bb556ab566130cc7936f06a69.tar.bz2 yosys-c6e16e1334dcbd8bb556ab566130cc7936f06a69.zip | |
_ABC macro will map and unmap to this new box
Diffstat (limited to 'techlibs/ice40')
| -rw-r--r-- | techlibs/ice40/arith_map.v | 10 | ||||
| -rw-r--r-- | techlibs/ice40/cells_map.v | 24 |
2 files changed, 34 insertions, 0 deletions
diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v index 4449fdc1b..6d45e4a6b 100644 --- a/techlibs/ice40/arith_map.v +++ b/techlibs/ice40/arith_map.v @@ -44,6 +44,15 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO); genvar i; generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice +`ifdef _ABC + \$__ICE40_CARRY_LUT4 carry ( + .A(AA[i]), + .B(BB[i]), + .CI(C[i]), + .CO(CO[i]), + .O(Y[i]) + ); +`else SB_CARRY carry ( .I0(AA[i]), .I1(BB[i]), @@ -63,6 +72,7 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO); .I3(C[i]), .O(Y[i]) ); +`endif end endgenerate assign X = AA ^ BB; diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v index 759549e30..5dca63e19 100644 --- a/techlibs/ice40/cells_map.v +++ b/techlibs/ice40/cells_map.v @@ -61,3 +61,27 @@ module \$lut (A, Y); endgenerate endmodule `endif + +`ifdef _ABC +module \$__ICE40_CARRY_LUT4 (output CO, O, input A, B, CI); + SB_CARRY carry ( + .I0(A), + .I1(B), + .CI(CI), + .CO(CO) + ); + SB_LUT4 #( + // I0: 1010 1010 1010 1010 + // I1: 1100 1100 1100 1100 + // I2: 1111 0000 1111 0000 + // I3: 1111 1111 0000 0000 + .LUT_INIT(16'b 0110_1001_1001_0110) + ) adder ( + .I0(1'b0), + .I1(A), + .I2(B), + .I3(CI), + .O(O) + ); +endmodule +`endif |