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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 12:18:32 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 12:18:32 -0700 |
| commit | 32eef26ee277b79736e135a8800625543dd6080a (patch) | |
| tree | 28cd6d5af904ddd2ec2772e2bd1d2378215c1dc7 /techlibs/ice40 | |
| parent | fe58790f3789a79b867660031d7e3e28cb3fff20 (diff) | |
| parent | c499dc3e73390c3bc9bf8045f2e4cad963c1fbad (diff) | |
| download | yosys-32eef26ee277b79736e135a8800625543dd6080a.tar.gz yosys-32eef26ee277b79736e135a8800625543dd6080a.tar.bz2 yosys-32eef26ee277b79736e135a8800625543dd6080a.zip | |
Merge remote-tracking branch 'origin/clifford/async2synclatch' into Sergey/tests_ice40
Diffstat (limited to 'techlibs/ice40')
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 2205be27d..c7f3bdad2 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -141,8 +141,16 @@ module SB_CARRY (output CO, input I0, I1, CI); assign CO = (I0 && I1) || ((I0 || I1) && CI); endmodule -(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *) -module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI); +(* abc_box_id = 1, lib_whitebox *) +module \$__ICE40_FULL_ADDER ( + (* abc_carry *) + output CO, + output O, + input A, + input B, + (* abc_carry *) + input CI +); SB_CARRY carry ( .I0(A), .I1(B), |