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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-11 21:13:40 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-11 21:13:40 -0700 |
| commit | 88d5185596a0cc8319658463a31b20644d90dd6b (patch) | |
| tree | 106f178d42a54403218f93cae2807d6e67981599 /techlibs/ice40/tests | |
| parent | 282cc77604a9a855c303869321d4179790b0b64b (diff) | |
| parent | c851dc13108021834533094a8a3236da6d9e0161 (diff) | |
| download | yosys-88d5185596a0cc8319658463a31b20644d90dd6b.tar.gz yosys-88d5185596a0cc8319658463a31b20644d90dd6b.tar.bz2 yosys-88d5185596a0cc8319658463a31b20644d90dd6b.zip | |
Merge remote-tracking branch 'origin/master' into eddie/fix_1262
Diffstat (limited to 'techlibs/ice40/tests')
| -rw-r--r-- | techlibs/ice40/tests/test_arith.ys | 9 |
1 files changed, 1 insertions, 8 deletions
diff --git a/techlibs/ice40/tests/test_arith.ys b/techlibs/ice40/tests/test_arith.ys index ddb80b700..160c767fb 100644 --- a/techlibs/ice40/tests/test_arith.ys +++ b/techlibs/ice40/tests/test_arith.ys @@ -1,5 +1,6 @@ read_verilog test_arith.v synth_ice40 +techmap -map ../cells_sim.v rename test gate read_verilog test_arith.v @@ -7,11 +8,3 @@ rename test gold miter -equiv -flatten -make_outputs gold gate miter sat -verify -prove trigger 0 -show-ports miter - -synth_ice40 -top gate - -read_verilog test_arith.v -rename test gold - -miter -equiv -flatten -make_outputs gold gate miter -sat -verify -prove trigger 0 -show-ports miter |