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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-08-18 11:47:46 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-08-18 11:47:46 +0200 |
| commit | 4a32e29445f65edd1726808a7353a9d0e2560c00 (patch) | |
| tree | 179544dd193fe72b3658269cb22a6eae66bee8a1 /techlibs/ice40/tests | |
| parent | 5f561bdcb1d562d6f975b4a27beca1b8b7af908f (diff) | |
| parent | 98a54353b7d893752d856b3726853d4921c6aa1f (diff) | |
| download | yosys-4a32e29445f65edd1726808a7353a9d0e2560c00.tar.gz yosys-4a32e29445f65edd1726808a7353a9d0e2560c00.tar.bz2 yosys-4a32e29445f65edd1726808a7353a9d0e2560c00.zip | |
Merge remote-tracking branch 'upstream/master' into anlogic_fixes
Diffstat (limited to 'techlibs/ice40/tests')
| -rw-r--r-- | techlibs/ice40/tests/test_arith.ys | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/techlibs/ice40/tests/test_arith.ys b/techlibs/ice40/tests/test_arith.ys index 160c767fb..ddb80b700 100644 --- a/techlibs/ice40/tests/test_arith.ys +++ b/techlibs/ice40/tests/test_arith.ys @@ -1,6 +1,5 @@ read_verilog test_arith.v synth_ice40 -techmap -map ../cells_sim.v rename test gate read_verilog test_arith.v @@ -8,3 +7,11 @@ rename test gold miter -equiv -flatten -make_outputs gold gate miter sat -verify -prove trigger 0 -show-ports miter + +synth_ice40 -top gate + +read_verilog test_arith.v +rename test gold + +miter -equiv -flatten -make_outputs gold gate miter +sat -verify -prove trigger 0 -show-ports miter |