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| author | Clifford Wolf <clifford@clifford.at> | 2019-02-21 18:56:01 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-02-21 18:56:01 +0100 |
| commit | 03aa3541aeff0ff372672f553c114fb4146c7858 (patch) | |
| tree | bd6c8e759d93f1a954ba2576857354b9a8fff638 /techlibs/ice40/tests/test_dsp_model.sh | |
| parent | 310b0a0ffa5ca48650c788c77eee0c8b91aa6bad (diff) | |
| parent | 893194689daee52ea870fef839c237c61e14c6c9 (diff) | |
| download | yosys-03aa3541aeff0ff372672f553c114fb4146c7858.tar.gz yosys-03aa3541aeff0ff372672f553c114fb4146c7858.tar.bz2 yosys-03aa3541aeff0ff372672f553c114fb4146c7858.zip | |
Merge pull request #786 from YosysHQ/pmgen
Pattern Matcher Generator and iCE40 DSP Mapper
Diffstat (limited to 'techlibs/ice40/tests/test_dsp_model.sh')
| -rw-r--r-- | techlibs/ice40/tests/test_dsp_model.sh | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/techlibs/ice40/tests/test_dsp_model.sh b/techlibs/ice40/tests/test_dsp_model.sh new file mode 100644 index 000000000..1bc0cc688 --- /dev/null +++ b/techlibs/ice40/tests/test_dsp_model.sh @@ -0,0 +1,11 @@ +#!/bin/bash +set -ex +sed 's/SB_MAC16/SB_MAC16_UUT/; /SB_MAC16_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v +cat /opt/lscc/iCEcube2.2017.01/verilog/sb_ice_syn.v > test_dsp_model_ref.v +for tb in testbench \ + testbench_comb_8x8_A testbench_comb_8x8_B testbench_comb_16x16 \ + testbench_seq_16x16_A testbench_seq_16x16_B +do + iverilog -s $tb -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v + vvp -N ./test_dsp_model +done |