diff options
| author | Miodrag Milanović <mmicko@gmail.com> | 2019-10-18 10:52:50 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-10-18 10:52:50 +0200 |
| commit | 0b0b0cc0d9e432f14218bb9ed643af3d06ab43dc (patch) | |
| tree | 24f6a3cd2c4fa19a41d90cd57b0908b668efeb21 /techlibs/ice40/synth_ice40.cc | |
| parent | 0d60902fd97bba4f231f8f600434b8a69562ffff (diff) | |
| parent | e0a67fce12647b4db7125d33264847c0a3781105 (diff) | |
| download | yosys-0b0b0cc0d9e432f14218bb9ed643af3d06ab43dc.tar.gz yosys-0b0b0cc0d9e432f14218bb9ed643af3d06ab43dc.tar.bz2 yosys-0b0b0cc0d9e432f14218bb9ed643af3d06ab43dc.zip | |
Merge branch 'master' into eddie/pr1352
Diffstat (limited to 'techlibs/ice40/synth_ice40.cc')
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 841f10244..b66c6bf57 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -245,7 +245,7 @@ struct SynthIce40Pass : public ScriptPass define = "-D ICE40_U"; else define = "-D ICE40_HX"; - run("read_verilog -icells " + define + " -lib +/ice40/cells_sim.v"); + run("read_verilog " + define + " -lib +/ice40/cells_sim.v"); run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str())); run("proc"); } @@ -349,6 +349,7 @@ struct SynthIce40Pass : public ScriptPass } if (!noabc) { if (abc == "abc9") { + run("read_verilog -icells -lib +/ice40/abc9_model.v"); int wire_delay; if (device_opt == "lp") wire_delay = 400; @@ -356,7 +357,7 @@ struct SynthIce40Pass : public ScriptPass wire_delay = 750; else wire_delay = 250; - run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)"); + run(abc + stringf(" -W %d -lut +/ice40/abc9_%s.lut -box +/ice40/abc9_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)"); } else run(abc + " -dress -lut 4", "(skip if -noabc)"); |