diff options
author | Eddie Hung <eddie@fpgeh.com> | 2020-03-12 12:57:01 -0700 |
---|---|---|
committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-02 07:14:08 -0700 |
commit | fdafb74eb77e33e9fa2b4e591804d1d02c122ff9 (patch) | |
tree | 49cd4fc4493b1ecfcf50aabda00aee1130124fa3 /techlibs/ice40/ice40_opt.cc | |
parent | 164dd0f6b298e416bd1ef882f21a4d0b5acfd039 (diff) | |
download | yosys-fdafb74eb77e33e9fa2b4e591804d1d02c122ff9.tar.gz yosys-fdafb74eb77e33e9fa2b4e591804d1d02c122ff9.tar.bz2 yosys-fdafb74eb77e33e9fa2b4e591804d1d02c122ff9.zip |
kernel: use more ID::*
Diffstat (limited to 'techlibs/ice40/ice40_opt.cc')
-rw-r--r-- | techlibs/ice40/ice40_opt.cc | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index 925ab31bb..7667f28cb 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -95,8 +95,8 @@ static void run_ice40_opts(Module *module) int count_zeros = 0, count_ones = 0; SigBit inbit[3] = { - cell->getPort("\\A"), - cell->getPort("\\B"), + cell->getPort(ID::A), + cell->getPort(ID::B), cell->getPort("\\CI") }; for (int i = 0; i < 3; i++) @@ -140,9 +140,9 @@ static void run_ice40_opts(Module *module) log_id(module), log_id(cell), log_signal(replacement_output)); cell->type = "$lut"; auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3))); - cell->setPort("\\A", { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort("\\I0")) }); - cell->setPort("\\Y", cell->getPort("\\O")); - cell->unsetPort("\\B"); + cell->setPort(ID::A, { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort("\\I0")) }); + cell->setPort(ID::Y, cell->getPort("\\O")); + cell->unsetPort(ID::B); cell->unsetPort("\\CI"); cell->unsetPort("\\I0"); cell->unsetPort("\\I3"); @@ -182,13 +182,13 @@ static void run_ice40_opts(Module *module) cell->setParam("\\LUT", cell->getParam("\\LUT_INIT")); cell->unsetParam("\\LUT_INIT"); - cell->setPort("\\A", SigSpec({ + cell->setPort(ID::A, SigSpec({ get_bit_or_zero(cell->getPort("\\I3")), get_bit_or_zero(cell->getPort("\\I2")), get_bit_or_zero(cell->getPort("\\I1")), get_bit_or_zero(cell->getPort("\\I0")) })); - cell->setPort("\\Y", cell->getPort("\\O")[0]); + cell->setPort(ID::Y, cell->getPort("\\O")[0]); cell->unsetPort("\\I0"); cell->unsetPort("\\I1"); cell->unsetPort("\\I2"); |