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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-28 11:55:51 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-01-28 11:55:51 -0800 |
| commit | 7939727d14f44b5d56ca3806d0907e9fceea2882 (patch) | |
| tree | 8237e2063e8e8b39bf0b8142c82a447f9c7ae3d6 /techlibs/ice40/ice40_opt.cc | |
| parent | 245b8c4ab64c5c3bd7b9f71f94316a76a2576fd1 (diff) | |
| parent | 6d27d4372730cb94306a4f314482459f9d527d7c (diff) | |
| download | yosys-7939727d14f44b5d56ca3806d0907e9fceea2882.tar.gz yosys-7939727d14f44b5d56ca3806d0907e9fceea2882.tar.bz2 yosys-7939727d14f44b5d56ca3806d0907e9fceea2882.zip | |
Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts
Unpermute LUT ordering for ice40/ecp5/xilinx
Diffstat (limited to 'techlibs/ice40/ice40_opt.cc')
| -rw-r--r-- | techlibs/ice40/ice40_opt.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index df10a2842..925ab31bb 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -139,8 +139,8 @@ static void run_ice40_opts(Module *module) log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n", log_id(module), log_id(cell), log_signal(replacement_output)); cell->type = "$lut"; - auto I3 = cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3)); - cell->setPort("\\A", { cell->getPort("\\I0"), inbit[0], inbit[1], I3 }); + auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3))); + cell->setPort("\\A", { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort("\\I0")) }); cell->setPort("\\Y", cell->getPort("\\O")); cell->unsetPort("\\B"); cell->unsetPort("\\CI"); |