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| author | Clifford Wolf <clifford@clifford.at> | 2018-12-05 08:59:21 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-12-05 08:59:21 -0800 |
| commit | 11323665aff4c4af612f12fb3dda5096ace26a7d (patch) | |
| tree | c7ae354013e44fe2500c7525a67c4ad9c5a39160 /techlibs/ice40/ice40_opt.cc | |
| parent | 615b30bd29b13011f3faaeb660e9738262b37f3a (diff) | |
| parent | 1719aa88acf9f6d52caa81384bc50237605157e3 (diff) | |
| download | yosys-11323665aff4c4af612f12fb3dda5096ace26a7d.tar.gz yosys-11323665aff4c4af612f12fb3dda5096ace26a7d.tar.bz2 yosys-11323665aff4c4af612f12fb3dda5096ace26a7d.zip | |
Merge pull request #716 from whitequark/ice40_unlut
Extract ice40_unlut pass from ice40_opt
Diffstat (limited to 'techlibs/ice40/ice40_opt.cc')
| -rw-r--r-- | techlibs/ice40/ice40_opt.cc | 15 |
1 files changed, 2 insertions, 13 deletions
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index 162740059..f528607d6 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -33,7 +33,7 @@ static SigBit get_bit_or_zero(const SigSpec &sig) return sig[0]; } -static void run_ice40_opts(Module *module, bool unlut_mode) +static void run_ice40_opts(Module *module) { pool<SigBit> optimized_co; vector<Cell*> sb_lut_cells; @@ -95,9 +95,6 @@ static void run_ice40_opts(Module *module, bool unlut_mode) inbits.append(get_bit_or_zero(cell->getPort("\\I3"))); sigmap.apply(inbits); - if (unlut_mode) - goto remap_lut; - if (optimized_co.count(inbits[0])) goto remap_lut; if (optimized_co.count(inbits[1])) goto remap_lut; if (optimized_co.count(inbits[2])) goto remap_lut; @@ -152,14 +149,10 @@ struct Ice40OptPass : public Pass { log(" opt_clean\n"); log(" while <changed design>\n"); log("\n"); - log("When called with the option -unlut, this command will transform all already\n"); - log("mapped SB_LUT4 cells back to logic.\n"); - log("\n"); } void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { string opt_expr_args = "-mux_undef -undriven"; - bool unlut_mode = false; log_header(design, "Executing ICE40_OPT pass (performing simple optimizations).\n"); log_push(); @@ -170,10 +163,6 @@ struct Ice40OptPass : public Pass { opt_expr_args += " -full"; continue; } - if (args[argidx] == "-unlut") { - unlut_mode = true; - continue; - } break; } extra_args(args, argidx, design); @@ -184,7 +173,7 @@ struct Ice40OptPass : public Pass { log_header(design, "Running ICE40 specific optimizations.\n"); for (auto module : design->selected_modules()) - run_ice40_opts(module, unlut_mode); + run_ice40_opts(module); Pass::call(design, "opt_expr " + opt_expr_args); Pass::call(design, "opt_merge"); |