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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-12 12:57:01 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-02 07:14:08 -0700 |
| commit | fdafb74eb77e33e9fa2b4e591804d1d02c122ff9 (patch) | |
| tree | 49cd4fc4493b1ecfcf50aabda00aee1130124fa3 /techlibs/ice40/ice40_ffinit.cc | |
| parent | 164dd0f6b298e416bd1ef882f21a4d0b5acfd039 (diff) | |
| download | yosys-fdafb74eb77e33e9fa2b4e591804d1d02c122ff9.tar.gz yosys-fdafb74eb77e33e9fa2b4e591804d1d02c122ff9.tar.bz2 yosys-fdafb74eb77e33e9fa2b4e591804d1d02c122ff9.zip | |
kernel: use more ID::*
Diffstat (limited to 'techlibs/ice40/ice40_ffinit.cc')
| -rw-r--r-- | techlibs/ice40/ice40_ffinit.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/ice40/ice40_ffinit.cc b/techlibs/ice40/ice40_ffinit.cc index c098736e9..29c999ff4 100644 --- a/techlibs/ice40/ice40_ffinit.cc +++ b/techlibs/ice40/ice40_ffinit.cc @@ -133,13 +133,13 @@ struct Ice40FfinitPass : public Pass { if (type_str.back() == 'S') { type_str.back() = 'R'; cell->type = type_str; - cell->setPort("\\R", cell->getPort("\\S")); - cell->unsetPort("\\S"); + cell->setPort("\\R", cell->getPort(ID::S)); + cell->unsetPort(ID::S); } else if (type_str.back() == 'R') { type_str.back() = 'S'; cell->type = type_str; - cell->setPort("\\S", cell->getPort("\\R")); + cell->setPort(ID::S, cell->getPort("\\R")); cell->unsetPort("\\R"); } |