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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-27 12:29:28 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-27 12:29:28 -0800 |
| commit | f2576c096cedf0974f237530a9d50e250bf117a3 (patch) | |
| tree | 3f5a0653615a125b0b51a2b135f5ac6d0b95794b /techlibs/ice40/ice40_ffinit.cc | |
| parent | b0605128b633f64b07107ba3a673f406e96d42ad (diff) | |
| parent | 9009b76a69b9e867f69295a8e555305925e83aeb (diff) | |
| download | yosys-f2576c096cedf0974f237530a9d50e250bf117a3.tar.gz yosys-f2576c096cedf0974f237530a9d50e250bf117a3.tar.bz2 yosys-f2576c096cedf0974f237530a9d50e250bf117a3.zip | |
Merge branch 'eddie/abc9_refactor' into eddie/abc9_required
Diffstat (limited to 'techlibs/ice40/ice40_ffinit.cc')
| -rw-r--r-- | techlibs/ice40/ice40_ffinit.cc | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/techlibs/ice40/ice40_ffinit.cc b/techlibs/ice40/ice40_ffinit.cc index 3089d8932..c098736e9 100644 --- a/techlibs/ice40/ice40_ffinit.cc +++ b/techlibs/ice40/ice40_ffinit.cc @@ -78,10 +78,12 @@ struct Ice40FfinitPass : public Pass { continue; if (initbits.count(bit)) { - if (initbits.at(bit) != val) - log_error("Conflicting init values for signal %s (%s = %s, %s = %s).\n", + if (initbits.at(bit) != val) { + log_warning("Conflicting init values for signal %s (%s = %s, %s = %s).\n", log_signal(bit), log_signal(SigBit(wire, i)), log_signal(val), log_signal(initbit_to_wire[bit]), log_signal(initbits.at(bit))); + initbits.at(bit) = State::Sx; + } continue; } @@ -114,6 +116,10 @@ struct Ice40FfinitPass : public Pass { continue; State val = initbits.at(bit_q); + + if (val == State::Sx) + continue; + handled_initbits.insert(bit_q); log("FF init value for cell %s (%s): %s = %c\n", log_id(cell), log_id(cell->type), |