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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-29 11:26:22 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-09-29 11:26:22 -0700 |
| commit | 8474c5b366660153cae03a9de4af8e1ed809856d (patch) | |
| tree | cd157ab16b528565ced19f422ffece1c6110f53e /techlibs/ice40/dsp_map.v | |
| parent | ce0631c371f69f0132ea9ee4bc8f5ee576dbb1a3 (diff) | |
| parent | b3d8a60cbd94176076f23c4ea6c94ec24e6773e0 (diff) | |
| download | yosys-8474c5b366660153cae03a9de4af8e1ed809856d.tar.gz yosys-8474c5b366660153cae03a9de4af8e1ed809856d.tar.bz2 yosys-8474c5b366660153cae03a9de4af8e1ed809856d.zip | |
Merge pull request #1359 from YosysHQ/xc7dsp
DSP inference for Xilinx (improved for ice40, initial support for ecp5)
Diffstat (limited to 'techlibs/ice40/dsp_map.v')
| -rw-r--r-- | techlibs/ice40/dsp_map.v | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/techlibs/ice40/dsp_map.v b/techlibs/ice40/dsp_map.v new file mode 100644 index 000000000..06fa73956 --- /dev/null +++ b/techlibs/ice40/dsp_map.v @@ -0,0 +1,34 @@ +module \$__MUL16X16 (input [15:0] A, input [15:0] B, output [31:0] Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + SB_MAC16 #( + .NEG_TRIGGER(1'b0), + .C_REG(1'b0), + .A_REG(1'b0), + .B_REG(1'b0), + .D_REG(1'b0), + .TOP_8x8_MULT_REG(1'b0), + .BOT_8x8_MULT_REG(1'b0), + .PIPELINE_16x16_MULT_REG1(1'b0), + .PIPELINE_16x16_MULT_REG2(1'b0), + .TOPOUTPUT_SELECT(2'b11), + .TOPADDSUB_LOWERINPUT(2'b0), + .TOPADDSUB_UPPERINPUT(1'b0), + .TOPADDSUB_CARRYSELECT(2'b0), + .BOTOUTPUT_SELECT(2'b11), + .BOTADDSUB_LOWERINPUT(2'b0), + .BOTADDSUB_UPPERINPUT(1'b0), + .BOTADDSUB_CARRYSELECT(2'b0), + .MODE_8x8(1'b0), + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED) + ) _TECHMAP_REPLACE_ ( + .A(A), + .B(B), + .O(Y), + ); +endmodule |