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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-14 16:08:54 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-15 09:18:07 -0700 |
| commit | 66b256d40e8762abd1c43e1c5d37d93fb57fc84e (patch) | |
| tree | cca64e5a17c708b099bbbbd1b6fcbaef34120488 /techlibs/greenpak4 | |
| parent | e9918365fd95efd95ce5c6165ca47eed9d29103c (diff) | |
| download | yosys-66b256d40e8762abd1c43e1c5d37d93fb57fc84e.tar.gz yosys-66b256d40e8762abd1c43e1c5d37d93fb57fc84e.tar.bz2 yosys-66b256d40e8762abd1c43e1c5d37d93fb57fc84e.zip | |
Fixed bug where GP_COUNTx_ADV would wrap even when KEEP was high
Diffstat (limited to 'techlibs/greenpak4')
| -rw-r--r-- | techlibs/greenpak4/cells_sim_digital.v | 94 |
1 files changed, 47 insertions, 47 deletions
diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v index 3ed80005b..84a5dd049 100644 --- a/techlibs/greenpak4/cells_sim_digital.v +++ b/techlibs/greenpak4/cells_sim_digital.v @@ -145,19 +145,18 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT, "RISING": begin always @(posedge CLK, posedge RST) begin - //Main counter if(KEEP) begin end else if(UP) count <= count + 1'd1; - else + if(count == 14'h3fff) + count <= COUNT_TO; + else begin count <= count - 1'd1; - //Wrapping - if(count == 0 && !UP) - count <= COUNT_TO; - if(count == 14'h3fff && UP) - count <= COUNT_TO; + if(count == 0) + count <= COUNT_TO; + end //Resets if(RST) begin @@ -173,19 +172,18 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT, "FALLING": begin always @(posedge CLK, negedge RST) begin - //Main counter if(KEEP) begin end else if(UP) count <= count + 1'd1; - else + if(count == 14'h3fff) + count <= COUNT_TO; + else begin count <= count - 1'd1; - //Wrapping - if(count == 0 && !UP) - count <= COUNT_TO; - if(count == 14'h3fff && UP) - count <= COUNT_TO; + if(count == 0) + count <= COUNT_TO; + end //Resets if(!RST) begin @@ -218,19 +216,18 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT, else begin - //Main counter if(KEEP) begin end else if(UP) count <= count + 1'd1; - else + if(count == 14'h3fff) + count <= COUNT_TO; + else begin count <= count - 1'd1; - //Wrapping - if(count == 0 && !UP) - count <= COUNT_TO; - if(count == 14'h3fff && UP) - count <= COUNT_TO; + if(count == 0) + count <= COUNT_TO; + end end @@ -289,14 +286,14 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT, end else if(UP) count <= count + 1'd1; - else + if(count == 8'hff) + count <= COUNT_TO; + else begin count <= count - 1'd1; - //Wrapping - if(count == 0 && !UP) - count <= COUNT_TO; - if(count == 8'hff && UP) - count <= COUNT_TO; + if(count == 0) + count <= COUNT_TO; + end //Resets if(RST) begin @@ -317,14 +314,14 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT, end else if(UP) count <= count + 1'd1; - else + if(count == 8'hff) + count <= COUNT_TO; + else begin count <= count - 1'd1; - //Wrapping - if(count == 0 && !UP) - count <= COUNT_TO; - if(count == 8'hff && UP) - count <= COUNT_TO; + if(count == 0) + count <= COUNT_TO; + end //Resets if(!RST) begin @@ -357,19 +354,18 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT, else begin - //Main counter if(KEEP) begin end else if(UP) count <= count + 1'd1; - else + if(count == 8'hff) + count <= COUNT_TO; + else begin count <= count - 1'd1; - //Wrapping - if(count == 0 && !UP) - count <= COUNT_TO; - if(count == 8'hff && UP) - count <= COUNT_TO; + if(count == 0) + count <= COUNT_TO; + end end @@ -737,20 +733,24 @@ module GP_PGEN(input wire nRST, input wire CLK, output reg OUT); parameter PATTERN_DATA = 16'h0; parameter PATTERN_LEN = 5'd16; + localparam COUNT_MAX = PATTERN_LEN - 1'h1; + reg[3:0] count = 0; always @(posedge CLK) begin - if(!nRST) - OUT <= PATTERN_DATA[0]; + if(!nRST) begin + count <= COUNT_MAX; + end else begin - count <= count + 1; - OUT <= PATTERN_DATA[count]; - - if( (count + 1) == PATTERN_LEN) - count <= 0; + count <= count - 1'h1; + if(count == 0) + count <= COUNT_MAX; end end + always @(*) + OUT = PATTERN_DATA[count]; + endmodule module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB); |