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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-12-15 07:17:07 +0800 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-12-15 07:17:07 +0800 |
| commit | 3491d338634b76639d46770c04f907ac60f19a96 (patch) | |
| tree | 3479ee1cb2a43e4b2f4f95e6b6e26eb7016c24b6 /techlibs/greenpak4 | |
| parent | ea787e6be3d8559dbf9994d73283d9a234273fe9 (diff) | |
| download | yosys-3491d338634b76639d46770c04f907ac60f19a96.tar.gz yosys-3491d338634b76639d46770c04f907ac60f19a96.tar.bz2 yosys-3491d338634b76639d46770c04f907ac60f19a96.zip | |
greenpak4: And another typo :(
Diffstat (limited to 'techlibs/greenpak4')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 65f4a6f70..25a49ac06 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -151,7 +151,7 @@ module GP_DCMPMUX(input SEL, input IN0, input IN1, input IN2, input IN3, output 2'b10: OUT <= IN1; 2'b01: OUT <= IN2; 2'b11: OUT <= IN3; - end + endcase end endmodule |