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author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-01-01 00:56:20 -0800 |
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committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-01-01 00:56:20 -0800 |
commit | 27a626ce9851f4f5832892d5bd6d60258af03ada (patch) | |
tree | 1a85533ecb66f1ce64f10abadb63c4c57f6af9b5 /techlibs/greenpak4 | |
parent | 5ffede5c0e81b682268129b79f305733e11242be (diff) | |
download | yosys-27a626ce9851f4f5832892d5bd6d60258af03ada.tar.gz yosys-27a626ce9851f4f5832892d5bd6d60258af03ada.tar.bz2 yosys-27a626ce9851f4f5832892d5bd6d60258af03ada.zip |
greenpak4: Added POUT to GP_COUNTx cells
Diffstat (limited to 'techlibs/greenpak4')
-rw-r--r-- | techlibs/greenpak4/cells_sim.v | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index dd21bdd50..57f27b44e 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -53,7 +53,7 @@ module GP_CLKBUF(input wire IN, output wire OUT); assign OUT = IN; endmodule -module GP_COUNT8(input CLK, input wire RST, output reg OUT); +module GP_COUNT8(input CLK, input wire RST, output reg OUT, output reg[7:0] POUT); parameter RESET_MODE = "RISING"; @@ -67,6 +67,7 @@ module GP_COUNT8(input CLK, input wire RST, output reg OUT); //Combinatorially output whenever we wrap low always @(*) begin OUT <= (count == 8'h0); + OUT <= count; end //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm. @@ -103,7 +104,7 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT); endmodule module GP_COUNT8_ADV(input CLK, input RST, output reg OUT, - input UP, input KEEP); + input UP, input KEEP, output reg[7:0] POUT); parameter RESET_MODE = "RISING"; parameter RESET_VALUE = "ZERO"; @@ -116,7 +117,7 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT, endmodule module GP_COUNT14_ADV(input CLK, input RST, output reg OUT, - input UP, input KEEP); + input UP, input KEEP, output reg[7:0] POUT); parameter RESET_MODE = "RISING"; parameter RESET_VALUE = "ZERO"; |