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| author | Diego <dhdezr@gmail.com> | 2019-04-12 23:40:02 -0500 |
|---|---|---|
| committer | Diego <dhdezr@gmail.com> | 2019-04-12 23:40:02 -0500 |
| commit | f9272fc56d7179f04a9f776bf056eedfc33dd358 (patch) | |
| tree | 1ea10dcfaed907f0796965292bd11479db61e469 /techlibs/gowin/dram.txt | |
| parent | db1a5ec6a2a437b296e7ba9de78afaf3b440327f (diff) | |
| download | yosys-f9272fc56d7179f04a9f776bf056eedfc33dd358.tar.gz yosys-f9272fc56d7179f04a9f776bf056eedfc33dd358.tar.bz2 yosys-f9272fc56d7179f04a9f776bf056eedfc33dd358.zip | |
GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow
Diffstat (limited to 'techlibs/gowin/dram.txt')
| -rw-r--r-- | techlibs/gowin/dram.txt | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/techlibs/gowin/dram.txt b/techlibs/gowin/dram.txt new file mode 100644 index 000000000..9db530251 --- /dev/null +++ b/techlibs/gowin/dram.txt @@ -0,0 +1,17 @@ +bram $__GW1NR_RAM16S4 + init 1 + abits 4 + dbits 4 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 1 + clocks 0 1 + clkpol 0 1 +endbram + +match $__GW1NR_RAM16S4 + make_outreg + min wports 1 +endmatch |