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| author | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2019-02-26 10:28:42 -0800 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-02-28 14:58:11 -0800 |
| commit | e2fc18f27b5e9f506724a486787c2106b9f7fb4f (patch) | |
| tree | efab7457784570035c54d67045292f6cda2f1447 /techlibs/gowin/arith_map.v | |
| parent | 68a693717347cefc057cbf1a1c8d0f66500dec4f (diff) | |
| download | yosys-e2fc18f27b5e9f506724a486787c2106b9f7fb4f.tar.gz yosys-e2fc18f27b5e9f506724a486787c2106b9f7fb4f.tar.bz2 yosys-e2fc18f27b5e9f506724a486787c2106b9f7fb4f.zip | |
Reduce amount of trailing whitespace in code base
Diffstat (limited to 'techlibs/gowin/arith_map.v')
| -rw-r--r-- | techlibs/gowin/arith_map.v | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/techlibs/gowin/arith_map.v b/techlibs/gowin/arith_map.v index 25e789e4a..e15de6423 100644 --- a/techlibs/gowin/arith_map.v +++ b/techlibs/gowin/arith_map.v @@ -25,24 +25,24 @@ module _80_gw1n_alu(A, B, CI, BI, X, Y, CO); parameter A_WIDTH = 1; parameter B_WIDTH = 1; parameter Y_WIDTH = 1; - + input [A_WIDTH-1:0] A; input [B_WIDTH-1:0] B; output [Y_WIDTH-1:0] X, Y; - + input CI, BI; output [Y_WIDTH-1:0] CO; - + wire _TECHMAP_FAIL_ = Y_WIDTH <= 2; - + wire [Y_WIDTH-1:0] A_buf, B_buf; \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); - + wire [Y_WIDTH-1:0] AA = A_buf; wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; wire [Y_WIDTH-1:0] C = {CO, CI}; - + genvar i; generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice ALU #(.ALU_MODE(32'b0)) |