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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-08-11 10:46:48 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-08-11 10:46:48 +0200 |
| commit | e609537e386535047f045bf0b8df7ebc5f23c469 (patch) | |
| tree | 00c82db8580e3b70875901db6fad9f3675f6a80d /techlibs/efinix | |
| parent | 8c8100e0df51401870fba13fccf5240461f76051 (diff) | |
| download | yosys-e609537e386535047f045bf0b8df7ebc5f23c469.tar.gz yosys-e609537e386535047f045bf0b8df7ebc5f23c469.tar.bz2 yosys-e609537e386535047f045bf0b8df7ebc5f23c469.zip | |
Fixed data width
Diffstat (limited to 'techlibs/efinix')
| -rw-r--r-- | techlibs/efinix/brams_map.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/efinix/brams_map.v b/techlibs/efinix/brams_map.v index 9ef01d026..3236f39a5 100644 --- a/techlibs/efinix/brams_map.v +++ b/techlibs/efinix/brams_map.v @@ -22,8 +22,8 @@ module \$__EFINIX_5K (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); localparam WRITEMODE_A = TRANSP2 ? "WRITE_FIRST" : "READ_FIRST"; EFX_RAM_5K #( - .READ_WIDTH(20), - .WRITE_WIDTH(20), + .READ_WIDTH(CFG_DBITS), + .WRITE_WIDTH(CFG_DBITS), .OUTPUT_REG(1'b0), .RCLK_POLARITY(1'b1), .RE_POLARITY(1'b1), |