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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 11:26:55 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 11:26:55 -0700 |
| commit | d672b1ddecf30cc7fd005ce7a06ab6c2d3dca1a5 (patch) | |
| tree | 46140158ab5a760da9280900e00240e5a1e6dca9 /techlibs/ecp5 | |
| parent | c7af71ecde65ad310e487a296b957678412fca74 (diff) | |
| parent | 509c353fe981c95ca667a637bf2b47477962a60b (diff) | |
| download | yosys-d672b1ddecf30cc7fd005ce7a06ab6c2d3dca1a5.tar.gz yosys-d672b1ddecf30cc7fd005ce7a06ab6c2d3dca1a5.tar.bz2 yosys-d672b1ddecf30cc7fd005ce7a06ab6c2d3dca1a5.zip | |
Merge remote-tracking branch 'origin/master' into xaig_arrival
Diffstat (limited to 'techlibs/ecp5')
| -rw-r--r-- | techlibs/ecp5/cells_sim.v | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 24de0c3c2..e2bf3c854 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -17,10 +17,12 @@ endmodule // --------------------------------------- (* abc_box_id=1, lib_whitebox *) module CCU2C( - (* abc_carry *) input CIN, + (* abc_carry *) + input CIN, input A0, B0, C0, D0, A1, B1, C1, D1, output S0, S1, - (* abc_carry *) output COUT + (* abc_carry *) + output COUT ); parameter [15:0] INIT0 = 16'h0000; parameter [15:0] INIT1 = 16'h0000; @@ -113,7 +115,8 @@ module TRELLIS_DPR16X4 ( input WRE, input WCK, input [3:0] RAD, - /* (* abc_arrival=<TODO> *) */ output [3:0] DO + /* (* abc_arrival=<TODO> *) */ + output [3:0] DO ); parameter WCKMUX = "WCK"; parameter WREMUX = "WRE"; |