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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-13 14:42:18 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 10:33:57 -0700 |
| commit | cea614f5aeb78446c663240103f94f10e71681e2 (patch) | |
| tree | 0dafedb815e1f6808dc6d867dbd86166ae22261b /techlibs/ecp5 | |
| parent | fdc340db8e93d5b50ef515a231f2fef18bdd8165 (diff) | |
| download | yosys-cea614f5aeb78446c663240103f94f10e71681e2.tar.gz yosys-cea614f5aeb78446c663240103f94f10e71681e2.tar.bz2 yosys-cea614f5aeb78446c663240103f94f10e71681e2.zip | |
ecp5: latches_map.v if *not* -asyncprld
Diffstat (limited to 'techlibs/ecp5')
| -rw-r--r-- | techlibs/ecp5/synth_ecp5.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index b99cbdf83..e5c1f7550 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -330,8 +330,8 @@ struct SynthEcp5Pass : public ScriptPass { if (abc2 || help_mode) run("abc", " (only if -abc2)"); - if (asyncprld || help_mode) - run("techmap -map +/ecp5/latches_map.v", "(only if -asyncprld)"); + if (!asyncprld || help_mode) + run("techmap -map +/ecp5/latches_map.v", "(skip if -asyncprld)"); if (abc9) { run("read_verilog -icells -lib -specify +/ecp5/abc9_model.v"); |