diff options
| author | David Shah <davey1576@gmail.com> | 2018-10-22 16:20:38 +0100 |
|---|---|---|
| committer | David Shah <davey1576@gmail.com> | 2018-10-22 16:20:38 +0100 |
| commit | b65932edc4a00860cafc04f962f2a08dd782b075 (patch) | |
| tree | 2f090d37faf48aa95c92de80fab5d2eb18b17082 /techlibs/ecp5 | |
| parent | 101f5234ff17c0395672a93da6ee10294212ad90 (diff) | |
| download | yosys-b65932edc4a00860cafc04f962f2a08dd782b075.tar.gz yosys-b65932edc4a00860cafc04f962f2a08dd782b075.tar.bz2 yosys-b65932edc4a00860cafc04f962f2a08dd782b075.zip | |
ecp5: Remove DSP parameters that don't work
Signed-off-by: David Shah <davey1576@gmail.com>
Diffstat (limited to 'techlibs/ecp5')
| -rw-r--r-- | techlibs/ecp5/cells_bb.v | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v index 7ef02ef6a..8644abecd 100644 --- a/techlibs/ecp5/cells_bb.v +++ b/techlibs/ecp5/cells_bb.v @@ -27,23 +27,16 @@ module MULT18X18D( parameter REG_INPUTB_CE = "CE0"; parameter REG_INPUTB_RST = "RST0"; parameter REG_INPUTC_CLK = "NONE"; - parameter REG_INPUTC_CE = "CE0"; - parameter REG_INPUTC_RST = "RST0"; parameter REG_PIPELINE_CLK = "NONE"; parameter REG_PIPELINE_CE = "CE0"; parameter REG_PIPELINE_RST = "RST0"; parameter REG_OUTPUT_CLK = "NONE"; - parameter REG_OUTPUT_CE = "CE0"; - parameter REG_OUTPUT_RST = "RST0"; parameter [127:0] CLK0_DIV = "ENABLED"; parameter [127:0] CLK1_DIV = "ENABLED"; parameter [127:0] CLK2_DIV = "ENABLED"; parameter [127:0] CLK3_DIV = "ENABLED"; - parameter HIGHSPEED_CLK = "NONE"; parameter [127:0] GSR = "ENABLED"; - parameter CAS_MATCH_REG = "FALSE"; parameter [127:0] SOURCEB_MODE = "B_SHIFT"; - parameter [127:0] MULT_BYPASS = "DISABLED"; parameter [127:0] RESETMODE = "SYNC"; endmodule @@ -68,11 +61,7 @@ module ALU54B( output SIGNEDR ); parameter REG_INPUTC0_CLK = "NONE"; - parameter REG_INPUTC0_CE = "CE0"; - parameter REG_INPUTC0_RST = "RST0"; parameter REG_INPUTC1_CLK = "NONE"; - parameter REG_INPUTC1_CE = "CE0"; - parameter REG_INPUTC1_RST = "RST0"; parameter REG_OPCODEOP0_0_CLK = "NONE"; parameter REG_OPCODEOP0_0_CE = "CE0"; parameter REG_OPCODEOP0_0_RST = "RST0"; @@ -87,20 +76,11 @@ module ALU54B( parameter REG_OPCODEIN_1_CE = "CE0"; parameter REG_OPCODEIN_1_RST = "RST0"; parameter REG_OUTPUT0_CLK = "NONE"; - parameter REG_OUTPUT0_CE = "CE0"; - parameter REG_OUTPUT0_RST = "RST0"; parameter REG_OUTPUT1_CLK = "NONE"; - parameter REG_OUTPUT1_CE = "CE0"; - parameter REG_OUTPUT1_RST = "RST0"; parameter REG_FLAG_CLK = "NONE"; - parameter REG_FLAG_CE = "CE0"; - parameter REG_FLAG_RST = "RST0"; parameter [127:0] MCPAT_SOURCE = "STATIC"; parameter [127:0] MASKPAT_SOURCE = "STATIC"; parameter MASK01 = "0x00000000000000"; - parameter REG_INPUTCFB_CLK = "NONE"; - parameter REG_INPUTCFB_CE = "CE0"; - parameter REG_INPUTCFB_RST = "RST0"; parameter [127:0] CLK0_DIV = "ENABLED"; parameter [127:0] CLK1_DIV = "ENABLED"; parameter [127:0] CLK2_DIV = "ENABLED"; @@ -110,7 +90,6 @@ module ALU54B( parameter RNDPAT = "0x00000000000000"; parameter [127:0] GSR = "ENABLED"; parameter [127:0] RESETMODE = "SYNC"; - parameter MULT9_MODE = "DISABLED"; parameter FORCE_ZERO_BARREL_SHIFT = "DISABLED"; parameter LEGACY = "DISABLED"; endmodule |