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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 10:48:44 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 10:48:44 -0700 |
| commit | 9fef1df3c1431cff2e097a10a502f77f04986a60 (patch) | |
| tree | f8b4c2b66db08476f3d623f7e1a1d6f57ec7b058 /techlibs/ecp5 | |
| parent | 4e11782cde412ce80ee8125dd9d55fe21945737f (diff) | |
| download | yosys-9fef1df3c1431cff2e097a10a502f77f04986a60.tar.gz yosys-9fef1df3c1431cff2e097a10a502f77f04986a60.tar.bz2 yosys-9fef1df3c1431cff2e097a10a502f77f04986a60.zip | |
Panic over. Model was elsewhere. Re-arrange for consistency
Diffstat (limited to 'techlibs/ecp5')
| -rw-r--r-- | techlibs/ecp5/synth_ecp5.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 1f5b1cb6b..67d2f483c 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -311,6 +311,7 @@ struct SynthEcp5Pass : public ScriptPass run("techmap " + techmap_args); if (abc9) { + run("read_verilog -icells -lib +/ecp5/abc_model.v"); if (nowidelut) run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200"); else |