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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-02 12:13:33 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-02 12:13:33 -0700 |
| commit | 7e8f7f4c59c96897159d32771d0c7179c5474281 (patch) | |
| tree | 1485f73353e8fe1a7825b41a9306b093ca93f774 /techlibs/ecp5/ecp5_gsr.cc | |
| parent | f76cb584940fa3217de28febdb103443b8a8cf37 (diff) | |
| parent | 4aa505d1b254b3fbb66af2d95b396a8f077da9d0 (diff) | |
| download | yosys-7e8f7f4c59c96897159d32771d0c7179c5474281.tar.gz yosys-7e8f7f4c59c96897159d32771d0c7179c5474281.tar.bz2 yosys-7e8f7f4c59c96897159d32771d0c7179c5474281.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys
Diffstat (limited to 'techlibs/ecp5/ecp5_gsr.cc')
| -rw-r--r-- | techlibs/ecp5/ecp5_gsr.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ecp5/ecp5_gsr.cc b/techlibs/ecp5/ecp5_gsr.cc index 8b8927d31..2bc714b6f 100644 --- a/techlibs/ecp5/ecp5_gsr.cc +++ b/techlibs/ecp5/ecp5_gsr.cc @@ -124,7 +124,7 @@ struct Ecp5GsrPass : public Pass { SigBit lsr = sigmap(sig_lsr[0]); if (!inverted_gsr.count(lsr)) continue; - cell->setParam(ID(SRMODE), Const("SYNC")); + cell->setParam(ID(SRMODE), Const("LSR_OVER_CE")); cell->unsetPort(ID(LSR)); } |