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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-22 14:37:27 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-04-22 14:37:27 -0700 |
| commit | 274098cce6133dfb9a5b0ad013e55119cb1741cf (patch) | |
| tree | 1055095be1f5ad79d6fde0dbc265f2f034a68c1c /techlibs/ecp5/ecp5_gsr.cc | |
| parent | cf14e186eb6c89696cd1db4b36697a4e80b6884a (diff) | |
| parent | 7f33a0294b7e6a299033cb4ee19bd86317737c08 (diff) | |
| download | yosys-274098cce6133dfb9a5b0ad013e55119cb1741cf.tar.gz yosys-274098cce6133dfb9a5b0ad013e55119cb1741cf.tar.bz2 yosys-274098cce6133dfb9a5b0ad013e55119cb1741cf.zip | |
Merge pull request #1983 from YosysHQ/eddie/use_default_param
Cleanup use of hard-coded default parameters in light of #1945
Diffstat (limited to 'techlibs/ecp5/ecp5_gsr.cc')
| -rw-r--r-- | techlibs/ecp5/ecp5_gsr.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/ecp5/ecp5_gsr.cc b/techlibs/ecp5/ecp5_gsr.cc index d1503f71f..1c69e1d79 100644 --- a/techlibs/ecp5/ecp5_gsr.cc +++ b/techlibs/ecp5/ecp5_gsr.cc @@ -81,7 +81,7 @@ struct Ecp5GsrPass : public Pass { for (auto cell : module->selected_cells()) { - if (!cell->hasParam(ID(GSR)) || cell->getParam(ID(GSR)).decode_string() != "AUTO") + if (cell->getParam(ID(GSR)).decode_string() != "AUTO") continue; bool gsren = found_gsr; @@ -114,9 +114,9 @@ struct Ecp5GsrPass : public Pass { { if (cell->type != ID(TRELLIS_FF)) continue; - if (!cell->hasParam(ID(GSR)) || cell->getParam(ID(GSR)).decode_string() != "ENABLED") + if (cell->getParam(ID(GSR)).decode_string() != "ENABLED") continue; - if (!cell->hasParam(ID(SRMODE)) || cell->getParam(ID(SRMODE)).decode_string() != "ASYNC") + if (cell->getParam(ID(SRMODE)).decode_string() != "ASYNC") continue; SigSpec sig_lsr = cell->getPort(ID(LSR)); if (GetSize(sig_lsr) < 1) |