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| author | rafaeltp <rafael.tp@gmail.com> | 2018-10-20 17:01:09 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-10-20 17:01:09 -0700 |
| commit | f25d0de6f80233b0af02067bea839bff19f62a3c (patch) | |
| tree | ac816776d2a0e78f9de10eb03d7e76e78d6b5b36 /techlibs/ecp5/cells_sim.v | |
| parent | c7770d9eeaf9fba0c9d07e7cce020fe89ec71600 (diff) | |
| parent | 23b69ca32b2ef93fc4b3f724099bfecdee0af869 (diff) | |
| download | yosys-f25d0de6f80233b0af02067bea839bff19f62a3c.tar.gz yosys-f25d0de6f80233b0af02067bea839bff19f62a3c.tar.bz2 yosys-f25d0de6f80233b0af02067bea839bff19f62a3c.zip | |
Merge pull request #1 from YosysHQ/master
updating
Diffstat (limited to 'techlibs/ecp5/cells_sim.v')
| -rw-r--r-- | techlibs/ecp5/cells_sim.v | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index e43632c64..6e4b0a5ac 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -265,16 +265,18 @@ module TRELLIS_IO( output O ); parameter DIR = "INPUT"; + reg T_pd; + always @(*) if (T === 1'bz) T_pd <= 1'b0; else T_pd <= T; generate if (DIR == "INPUT") begin assign B = 1'bz; assign O = B; end else if (DIR == "OUTPUT") begin - assign B = T ? 1'bz : I; + assign B = T_pd ? 1'bz : I; assign O = 1'bx; - end else if (DIR == "INOUT") begin - assign B = T ? 1'bz : I; + end else if (DIR == "BIDIR") begin + assign B = T_pd ? 1'bz : I; assign O = B; end else begin ERROR_UNKNOWN_IO_MODE error(); |