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| author | David Shah <davey1576@gmail.com> | 2018-07-13 14:08:42 +0200 |
|---|---|---|
| committer | David Shah <davey1576@gmail.com> | 2018-07-13 14:08:42 +0200 |
| commit | 1def34f2a64603a3186dc50460fe964f1f197a43 (patch) | |
| tree | 802b61e363ee82d37ac07156690808d95d5aed50 /techlibs/ecp5/cells_sim.v | |
| parent | b1b9e23f949410fe7c337491a5813f2741a5d9a1 (diff) | |
| download | yosys-1def34f2a64603a3186dc50460fe964f1f197a43.tar.gz yosys-1def34f2a64603a3186dc50460fe964f1f197a43.tar.bz2 yosys-1def34f2a64603a3186dc50460fe964f1f197a43.zip | |
ecp5: Adding DRAM map
Signed-off-by: David Shah <davey1576@gmail.com>
Diffstat (limited to 'techlibs/ecp5/cells_sim.v')
| -rw-r--r-- | techlibs/ecp5/cells_sim.v | 37 |
1 files changed, 36 insertions, 1 deletions
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 54006218f..06e6133a7 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -52,7 +52,7 @@ module TRELLIS_RAM16X2 ( input RAD0, RAD1, RAD2, RAD3, output DO0, DO1 ); - parameter WCKMUX = "WCK"; + parameter WCKMUX = "WCK"; parameter WREMUX = "WRE"; parameter INITVAL_0 = 16'h0000; parameter INITVAL_1 = 16'h0000; @@ -87,6 +87,41 @@ endmodule // --------------------------------------- +module TRELLIS_DPR16X4 ( + input [3:0] DI, + input [3:0] WAD, + input WRE, WCK, + input [3:0] RAD, + output [3:0] DO +); + parameter WCKMUX = "WCK"; + parameter WREMUX = "WRE"; + parameter [63:0] INITVAL = 64'h0000000000000000; + + reg [3:0] mem[15:0]; + + integer i; + initial begin + for (i = 0; i < 16; i = i + 1) + mem[i] <= INITVAL[4*i :+ 4]; + end + + wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK; + + wire muxwre = (WREMUX == "1") ? 1'b1 : + (WREMUX == "0") ? 1'b0 : + (WREMUX == "INV") ? ~WRE : + WRE; + + always @(posedge muxwck) + if (muxwre) + mem[WAD] <= DI; + + assign DO = mem[RAD]; +endmodule + +// --------------------------------------- + module DPR16X4C ( input [3:0] DI, input WCK, WRE, |